From patchwork Fri Dec 3 08:46:27 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 376941 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB38kfb5000377 for ; Fri, 3 Dec 2010 08:46:41 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751802Ab0LCIqj (ORCPT ); Fri, 3 Dec 2010 03:46:39 -0500 Received: from eu1sys200aog115.obsmtp.com ([207.126.144.139]:53590 "EHLO eu1sys200aog115.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751777Ab0LCIqj (ORCPT ); Fri, 3 Dec 2010 03:46:39 -0500 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob115.postini.com ([207.126.147.11]) with SMTP ID DSNKTPiuaxqxNw0zFhxiJ7D5iY0EOj41GJkX@postini.com; Fri, 03 Dec 2010 08:46:39 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 428648F; Fri, 3 Dec 2010 08:46:31 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id F270A14D0; Fri, 3 Dec 2010 08:46:30 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 61BD0A809F; Fri, 3 Dec 2010 09:46:27 +0100 (CET) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.2.254.0; Fri, 3 Dec 2010 09:46:30 +0100 From: Linus Walleij To: , Cc: Ulf Hansson , Linus Walleij Subject: [PATCH] mmci: corrected calculation of clock div for ux500 v2 Date: Fri, 3 Dec 2010 09:46:27 +0100 Message-ID: <1291365987-17882-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Fri, 03 Dec 2010 08:46:41 +0000 (UTC) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 7567872..9bd3a18 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -51,6 +51,7 @@ static unsigned int fmax = 515633; * @broken_blockend_dma: the MCI_DATABLOCKEND is broken on the hardware when * using DMA. * @sdio: variant supports SDIO + * @st_clkdiv: true if using a ST-specific clock divider algorithm */ struct variant_data { unsigned int clkreg; @@ -61,6 +62,7 @@ struct variant_data { bool broken_blockend; bool broken_blockend_dma; bool sdio; + bool st_clkdiv; }; static struct variant_data variant_arm = { @@ -86,7 +88,9 @@ static struct variant_data variant_ux500 = { .datalength_bits = 24, .broken_blockend = true, .sdio = true, + .st_clkdiv = true, }; + /* * This must be called with host->lock held */ @@ -97,9 +101,30 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) if (desired) { if (desired >= host->mclk) { - clk = MCI_CLK_BYPASS; + /* + * The ST clock divider does not like the bypass bit, + * even though it's available. Instead the datasheet + * recommends setting the divider to zero. + */ + if (!variant->st_clkdiv) + clk = MCI_CLK_BYPASS; host->cclk = host->mclk; + } else if (variant->st_clkdiv) { + /* + * DB8500 TRM says f = mclk / (clkdiv + 2) + * => clkdiv = (mclk / f) - 2 + * Round the divider up so we don't exceed the max + * frequency + */ + clk = DIV_ROUND_UP(host->mclk, desired) - 2; + if (clk >= 256) + clk = 255; + host->cclk = host->mclk / (clk + 2); } else { + /* + * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) + * => clkdiv = mclk / (2 * f) - 1 + */ clk = host->mclk / (2 * desired) - 1; if (clk >= 256) clk = 255;