From patchwork Wed Dec 8 09:33:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sahitya Tummala X-Patchwork-Id: 390252 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB89XgjV001541 for ; Wed, 8 Dec 2010 09:34:01 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752408Ab0LHJeB (ORCPT ); Wed, 8 Dec 2010 04:34:01 -0500 Received: from wolverine01.qualcomm.com ([199.106.114.254]:17595 "EHLO wolverine01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751132Ab0LHJeA (ORCPT ); Wed, 8 Dec 2010 04:34:00 -0500 X-IronPort-AV: E=McAfee;i="5400,1158,6190"; a="65925964" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine01.qualcomm.com with ESMTP/TLS/ADH-AES256-SHA; 08 Dec 2010 01:33:50 -0800 Received: from stummala-linux.in.qualcomm.com (pdmz-snip-v218.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id C4E5910004D2; Wed, 8 Dec 2010 01:33:40 -0800 (PST) From: Sahitya Tummala To: cjb@laptop.org, dwalker@codeaurora.org, linux-mmc@vger.kernel.org Cc: san@google.com, linux-arm-msm@vger.kernel.org, Sahitya Tummala Subject: [PATCH V2 3/5] mmc: msm_sdcc: Reset SDCC in case of data transfer errors Date: Wed, 8 Dec 2010 15:03:05 +0530 Message-Id: <1291800787-24757-3-git-send-email-stummala@codeaurora.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1291800787-24757-1-git-send-email-stummala@codeaurora.org> References: <1291800787-24757-1-git-send-email-stummala@codeaurora.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Wed, 08 Dec 2010 09:34:02 +0000 (UTC) diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index 67f536c..81ed16f 100644 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c @@ -44,6 +44,7 @@ #include #include #include +#include #include "msm_sdcc.h" @@ -126,6 +127,40 @@ static void msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c); +static void msmsdcc_reset_and_restore(struct msmsdcc_host *host) +{ + u32 mci_clk = 0; + u32 mci_mask0 = 0; + int ret = 0; + + /* Save the controller state */ + mci_clk = readl(host->base + MMCICLOCK); + mci_mask0 = readl(host->base + MMCIMASK0); + + /* Reset the controller */ + ret = clk_reset(host->clk, CLK_RESET_ASSERT); + if (ret) + pr_err("%s: Clock assert failed at %u Hz with err %d\n", + mmc_hostname(host->mmc), host->clk_rate, ret); + + ret = clk_reset(host->clk, CLK_RESET_DEASSERT); + if (ret) + pr_err("%s: Clock deassert failed at %u Hz with err %d\n", + mmc_hostname(host->mmc), host->clk_rate, ret); + + pr_info("%s: Controller has been re-initialiazed\n", + mmc_hostname(host->mmc)); + + /* Restore the contoller state */ + writel(host->pwr, host->base + MMCIPOWER); + writel(mci_clk, host->base + MMCICLOCK); + writel(mci_mask0, host->base + MMCIMASK0); + ret = clk_set_rate(host->clk, host->clk_rate); + if (ret) + pr_err("%s: Failed to set clk rate %u Hz (%d)\n", + mmc_hostname(host->mmc), host->clk_rate, ret); +} + static void msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq) { @@ -223,6 +258,8 @@ msmsdcc_dma_complete_tlet(unsigned long data) pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n", err.flush[0], err.flush[1], err.flush[2], err.flush[3], err.flush[4], err.flush[5]); + + msmsdcc_reset_and_restore(host); if (!mrq->data->error) mrq->data->error = -EIO; } @@ -723,6 +760,7 @@ static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status) msm_dmov_stop_cmd(host->dma.channel, &host->dma.hdr, 0); else if (host->curr.data) { /* Non DMA */ + msmsdcc_reset_and_restore(host); msmsdcc_stop_data(host); msmsdcc_request_end(host, cmd->mrq); } else { /* host->data == NULL */ @@ -771,6 +809,7 @@ msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status, msm_dmov_stop_cmd(host->dma.channel, &host->dma.hdr, 0); else { + msmsdcc_reset_and_restore(host); if (host->curr.data) msmsdcc_stop_data(host); if (!data->stop)