From patchwork Fri Apr 15 10:38:55 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arindam Nath X-Patchwork-Id: 710541 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3FAeWtd027584 for ; Fri, 15 Apr 2011 10:41:05 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755742Ab1DOKlF (ORCPT ); Fri, 15 Apr 2011 06:41:05 -0400 Received: from mail-px0-f179.google.com ([209.85.212.179]:43166 "EHLO mail-px0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755735Ab1DOKlE (ORCPT ); Fri, 15 Apr 2011 06:41:04 -0400 Received: by pxi2 with SMTP id 2so1520921pxi.10 for ; Fri, 15 Apr 2011 03:41:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:cc:subject:date:message-id :x-mailer:in-reply-to:references; bh=9zZF2ScSVwp3HOEYxdYMHfYMoVCGGtyVJZAkvJVq/wE=; b=GD90agGSwRaKk80o6jfcyq6WpA4q83nqBnzuUZb3sffL4sOB+Xj4uBgg8WoRobkkhS dTsJghmy1dn/uSthhhaibNftt9tXjjoVplNBl6Gea9qrX8wZMG92bymi24ZdsMzNqN+q b/+0SnQCOJxM0R4PLFn+/eDsWj/av9EUkrORE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; b=DxsoWgkUPvaSpENd+DfIddKOx5b6B74leCxinZwpX5S4Vezy/MuKbvKbWQPb5O6Snc bxXGvYvwTB1rHAVu/TLgR9OyoSHq0G801CFv930WcgmnhTzF0dsvYkhwS/WudXB+bQ2y 9vhkCIpHc5fLjMW7wEyZbAHKG2BANO3uGmthw= Received: by 10.68.24.229 with SMTP id x5mr1809860pbf.55.1302864063908; Fri, 15 Apr 2011 03:41:03 -0700 (PDT) Received: from localhost ([122.167.17.41]) by mx.google.com with ESMTPS id v8sm366699pbk.95.2011.04.15.03.40.55 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 15 Apr 2011 03:41:03 -0700 (PDT) From: Arindam Nath To: cjb@laptop.org Cc: linux-mmc@vger.kernel.org, subhashj@codeaurora.org, prakity@marvell.com, zhangfei.gao@gmail.com, henry.su@amd.com, aaron.lu@amd.com, anath.amd@gmail.com, Arindam Nath Subject: [PATCH v3 05/12] mmc: sdhci: reset sdclk before setting high speed enable Date: Fri, 15 Apr 2011 16:08:55 +0530 Message-Id: <1302863942-1774-6-git-send-email-arindam.nath@amd.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1302863942-1774-1-git-send-email-arindam.nath@amd.com> References: <1302863942-1774-1-git-send-email-arindam.nath@amd.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 15 Apr 2011 10:41:05 +0000 (UTC) As per Host Controller spec v3.00, we reset SDCLK before setting High Speed Enable, and then set it back to avoid generating clock gliches. Before enabling SDCLK again, we make sure the clock is stable, so we use sdhci_set_clock(). Signed-off-by: Arindam Nath --- drivers/mmc/host/sdhci.c | 27 ++++++++++++++++++++++++--- 1 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index fa18b4b..858cdb8 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1286,13 +1286,12 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) else ctrl &= ~SDHCI_CTRL_HISPD; - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); - if (host->version >= SDHCI_SPEC_300) { u16 ctrl_2; ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); /* * We only need to set Driver Strength if the * preset value enable is not set. @@ -1304,8 +1303,30 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + } else { + /* + * According to SDHC Spec v3.00, if the Preset Value + * Enable in the Host Control 2 register is set, we + * need to reset SD Clock Enable before changing High + * Speed Enable to avoid generating clock gliches. + */ + u16 clk; + unsigned int clock; + + /* Reset SD Clock Enable */ + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); + + /* Re-enable SD Clock */ + clock = host->clock; + host->clock = 0; + sdhci_set_clock(host, clock); } - } + } else + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); /* * Some (ENE) controllers go apeshit on some ios operation,