From patchwork Wed Apr 20 09:30:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arindam Nath X-Patchwork-Id: 721331 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3K9WGP0031314 for ; Wed, 20 Apr 2011 09:32:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753748Ab1DTJcQ (ORCPT ); Wed, 20 Apr 2011 05:32:16 -0400 Received: from mail-pv0-f174.google.com ([74.125.83.174]:33405 "EHLO mail-pv0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753597Ab1DTJcP (ORCPT ); Wed, 20 Apr 2011 05:32:15 -0400 Received: by pvg12 with SMTP id 12so288395pvg.19 for ; Wed, 20 Apr 2011 02:32:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:cc:subject:date:message-id :x-mailer:in-reply-to:references; bh=Q0SQiXb/w0pWVckWhZBAybyWajEG9OVZsdEg5mOmc7k=; b=BfdE6+otfOyJ3vT1/iJ0blC848o+BQx7B9KBj4hrQQzDYY3vZy09LsoWYDUqyOoTcI A12/NEk8EQvewIwOUy29efZ9iIjAZIPMRGJHwC2a2DUex0Ms1wCQpTWiWYgvWY9fJCbx 1HeLSrT/zQ1sIHjKrbTJ4ZENqKeYaJFbH1gmM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; b=Xmdigoj5H/Gy1jI7Z7QHMVMAiILcKNkU1KPsdJrUUHpXn9s0DmAoRcdViEg4GRvWnn OexYOMAb8to0GtY/MOrdOiFtopaVInMw8LAaLxn0zZ9H5AbLMDzt8ApyZ6OqTtD+P1D1 CYihVAWhTBe5oT1gxFGHsuTKxcOZ9nMGYt9Pw= Received: by 10.68.41.168 with SMTP id g8mr10005955pbl.194.1303291935378; Wed, 20 Apr 2011 02:32:15 -0700 (PDT) Received: from localhost ([122.167.17.41]) by mx.google.com with ESMTPS id a3sm523973pbt.57.2011.04.20.02.32.08 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 20 Apr 2011 02:32:14 -0700 (PDT) From: Arindam Nath To: cjb@laptop.org Cc: linux-mmc@vger.kernel.org, prakity@marvell.com, subhashj@codeaurora.org, zhangfei.gao@gmail.com, henry.su@amd.com, aaron.lu@amd.com, anath.amd@gmail.com, Arindam Nath Subject: [PATCH v3 04/11] mmc: sdhci: reset sdclk before setting high speed enable Date: Wed, 20 Apr 2011 15:00:54 +0530 Message-Id: <1303291861-1788-5-git-send-email-arindam.nath@amd.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1303291861-1788-1-git-send-email-arindam.nath@amd.com> References: <1303291861-1788-1-git-send-email-arindam.nath@amd.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 20 Apr 2011 09:32:16 +0000 (UTC) As per Host Controller spec v3.00, we reset SDCLK before setting High Speed Enable, and then set it back to avoid generating clock gliches. Before enabling SDCLK again, we make sure the clock is stable, so we use sdhci_set_clock(). Signed-off-by: Arindam Nath --- drivers/mmc/host/sdhci.c | 27 ++++++++++++++++++++++++--- 1 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index faf332f..175f858 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1237,13 +1237,12 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) else ctrl &= ~SDHCI_CTRL_HISPD; - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); - if (host->version >= SDHCI_SPEC_300) { u16 ctrl_2; ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); /* * We only need to set Driver Strength if the * preset value enable is not set. @@ -1255,8 +1254,30 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + } else { + /* + * According to SDHC Spec v3.00, if the Preset Value + * Enable in the Host Control 2 register is set, we + * need to reset SD Clock Enable before changing High + * Speed Enable to avoid generating clock gliches. + */ + u16 clk; + unsigned int clock; + + /* Reset SD Clock Enable */ + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); + + /* Re-enable SD Clock */ + clock = host->clock; + host->clock = 0; + sdhci_set_clock(host, clock); } - } + } else + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1); /* * Some (ENE) controllers go apeshit on some ios operation,