From patchwork Tue Apr 26 05:34:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sahitya Tummala X-Patchwork-Id: 731462 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3Q5ZBg1017158 for ; Tue, 26 Apr 2011 05:35:26 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753031Ab1DZFfZ (ORCPT ); Tue, 26 Apr 2011 01:35:25 -0400 Received: from wolverine01.qualcomm.com ([199.106.114.254]:19987 "EHLO wolverine01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752615Ab1DZFfY (ORCPT ); Tue, 26 Apr 2011 01:35:24 -0400 X-IronPort-AV: E=McAfee;i="5400,1158,6327"; a="87818293" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine01.qualcomm.com with ESMTP/TLS/ADH-AES256-SHA; 25 Apr 2011 22:35:24 -0700 Received: from stummala-linux.in.qualcomm.com (pdmz-snip-v218.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id AB4EF10004DF; Mon, 25 Apr 2011 22:35:04 -0700 (PDT) From: Sahitya Tummala To: davidb@codeaurora.org, dwalker@fifo99.com, bryanh@codeaurora.org Cc: linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, san@google.com, Sahitya Tummala , Murali Palnati Subject: [PATCH 3/7] mmc: msm_sdcc: Enable SDC host->clk only after setting the rate. Date: Tue, 26 Apr 2011 11:04:22 +0530 Message-Id: <1303796066-6784-3-git-send-email-stummala@codeaurora.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1303796066-6784-1-git-send-email-stummala@codeaurora.org> References: <1303796066-6784-1-git-send-email-stummala@codeaurora.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 26 Apr 2011 05:35:26 +0000 (UTC) For clocks that support rates which can be set (most clocks other than _pclk AHB clocks), a rate must be set using clk_set_rate() before the clock is enabled for the first time with clk_enable(). Subsequent calls to clk_enable() need not be preceded with the clk_set_rate() calls unless we wish to change the clock rate that is set previously. SDC host->clk is currently enabled without setting the clock rate even once. This patch fixes this, by ensuring that the clock rate for this clock is first set before enabling the clock. Signed-off-by: Murali Palnati Signed-off-by: Sahitya Tummala --- drivers/mmc/host/msm_sdcc.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index 66ef5c3..3446cdd 100644 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c @@ -1238,17 +1238,17 @@ msmsdcc_probe(struct platform_device *pdev) goto pclk_put; } - /* Enable clocks */ - ret = msmsdcc_enable_clocks(host); - if (ret) - goto clk_put; - ret = clk_set_rate(host->clk, msmsdcc_fmin); if (ret) { pr_err("%s: Clock rate set failed (%d)\n", __func__, ret); - goto clk_disable; + goto clk_put; } + /* Enable clocks */ + ret = msmsdcc_enable_clocks(host); + if (ret) + goto clk_put; + host->pclk_rate = clk_get_rate(host->pclk); host->clk_rate = clk_get_rate(host->clk);