From patchwork Mon May 2 12:37:01 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sahitya Tummala X-Patchwork-Id: 747162 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p42CbFW3025958 for ; Mon, 2 May 2011 12:37:15 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755354Ab1EBMhO (ORCPT ); Mon, 2 May 2011 08:37:14 -0400 Received: from wolverine02.qualcomm.com ([199.106.114.251]:39596 "EHLO wolverine02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754579Ab1EBMhO (ORCPT ); Mon, 2 May 2011 08:37:14 -0400 X-IronPort-AV: E=McAfee;i="5400,1158,6333"; a="88767668" Received: from pdmz-css-vrrp.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.130]) by wolverine02.qualcomm.com with ESMTP/TLS/ADH-AES256-SHA; 02 May 2011 05:37:13 -0700 Received: from stummala-linux.in.qualcomm.com (pdmz-snip-v218.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 214BE10004A2; Mon, 2 May 2011 05:36:52 -0700 (PDT) From: Sahitya Tummala To: davidb@codeaurora.org, bryanh@codeaurora.org, dwalker@fifo99.com Cc: linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, san@google.com, Sahitya Tummala , Murali Palnati Subject: [PATCH V2 3/7] mmc: msm_sdcc: Enable SDC host->clk only after setting the rate. Date: Mon, 2 May 2011 18:07:01 +0530 Message-Id: <1304339821-8421-1-git-send-email-stummala@codeaurora.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1303796066-6784-3-git-send-email-stummala@codeaurora.org> References: <1303796066-6784-3-git-send-email-stummala@codeaurora.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 02 May 2011 12:37:28 +0000 (UTC) For clocks that support rates which can be set (most clocks other than _pclk AHB clocks), a rate must be set using clk_set_rate() before the clock is enabled for the first time with clk_enable(). Subsequent calls to clk_enable() need not be preceded with the clk_set_rate() calls unless we wish to change the clock rate that is set previously. SDC host->clk is currently enabled without setting the clock rate even once. This patch fixes this, by ensuring that the clock rate for this clock is first set before enabling the clock. Signed-off-by: Murali Palnati Signed-off-by: Sahitya Tummala --- drivers/mmc/host/msm_sdcc.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index 66ef5c3..3446cdd 100644 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c @@ -1238,17 +1238,17 @@ msmsdcc_probe(struct platform_device *pdev) goto pclk_put; } - /* Enable clocks */ - ret = msmsdcc_enable_clocks(host); - if (ret) - goto clk_put; - ret = clk_set_rate(host->clk, msmsdcc_fmin); if (ret) { pr_err("%s: Clock rate set failed (%d)\n", __func__, ret); - goto clk_disable; + goto clk_put; } + /* Enable clocks */ + ret = msmsdcc_enable_clocks(host); + if (ret) + goto clk_put; + host->pclk_rate = clk_get_rate(host->pclk); host->clk_rate = clk_get_rate(host->clk);