From patchwork Fri May 6 09:14:06 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 761282 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p469FGxf023710 for ; Fri, 6 May 2011 09:15:19 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755676Ab1EFJPO (ORCPT ); Fri, 6 May 2011 05:15:14 -0400 Received: from smtp.nokia.com ([147.243.128.24]:45099 "EHLO mgw-da01.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755344Ab1EFJPG (ORCPT ); Fri, 6 May 2011 05:15:06 -0400 Received: from nokia.com (localhost [127.0.0.1]) by mgw-da01.nokia.com (Switch-3.4.4/Switch-3.4.3) with ESMTP id p469ES9N017628; Fri, 6 May 2011 12:14:59 +0300 Received: from localhost.localdomain ([helruo-dhcp022207.ntc.nokia.com [172.21.22.207]]) by mgw-da01.nokia.com with RELAY id p469EHdx017428 ; Fri, 6 May 2011 12:14:39 +0300 From: Adrian Hunter To: Tony Lindgren Cc: Madhusudhan Chikkature , linux-omap Mailing List , linux-mmc Mailing List , linux-arm Mailing List , Andy Shevchenko , Adrian Hunter Subject: [PATCH V2 07/16] mmc: omap_hsmmc: fix few bugs when set the clock divisor Date: Fri, 6 May 2011 12:14:06 +0300 Message-Id: <1304673255-31634-8-git-send-email-adrian.hunter@nokia.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1304673255-31634-1-git-send-email-adrian.hunter@nokia.com> References: <1304673255-31634-1-git-send-email-adrian.hunter@nokia.com> X-Nokia-AV: Clean Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 06 May 2011 09:15:19 +0000 (UTC) From: Andy Shevchenko There are two pieces of code which similar, but not the same. Each of them contains a bug. The SYSCTL register should be read before write in the omap_hsmmc_context_restore() to remain the state of the reserved bits. Before set the clock divisor and DTO bits the value from the SYSCTL register should be masked properly. We were lucky to have no problems with DTO bits. So, make sure we have clear DTO bits properly in the omap_hsmmc_set_ios(). Additionally get rid of msleep(1). The actual time rare higher than 30us on OMAP 3630. The result pieces of code are split to omap_hsmmc_set_clock() function. Signed-off-by: Andy Shevchenko Signed-off-by: Adrian Hunter --- drivers/mmc/host/omap_hsmmc.c | 59 +++++++++++++++++++--------------------- 1 files changed, 28 insertions(+), 31 deletions(-) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 915d08b..dd0d9d5 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -607,6 +607,32 @@ static u16 calc_divisor(struct mmc_ios *ios) return dsor; } +static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) +{ + struct mmc_ios *ios = &host->mmc->ios; + unsigned long regval; + unsigned long timeout; + + dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); + + omap_hsmmc_stop_clock(host); + + regval = OMAP_HSMMC_READ(host->base, SYSCTL); + regval = regval & ~(CLKD_MASK | DTO_MASK); + regval = regval | (calc_divisor(ios) << 6) | (DTO << 16); + OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); + OMAP_HSMMC_WRITE(host->base, SYSCTL, + OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); + + /* Wait till the ICS bit is set */ + timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); + while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS + && time_before(jiffies, timeout)) + cpu_relax(); + + omap_hsmmc_start_clock(host); +} + #ifdef CONFIG_PM /* @@ -697,19 +723,7 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) break; } - omap_hsmmc_stop_clock(host); - - OMAP_HSMMC_WRITE(host->base, SYSCTL, - (calc_divisor(ios) << 6) | (DTO << 16)); - OMAP_HSMMC_WRITE(host->base, SYSCTL, - OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); - - timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); - while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS - && time_before(jiffies, timeout)) - ; - - omap_hsmmc_start_clock(host); + omap_hsmmc_set_clock(host); con = OMAP_HSMMC_READ(host->base, CON); if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) @@ -1540,8 +1554,6 @@ static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct omap_hsmmc_host *host = mmc_priv(mmc); - unsigned long regval; - unsigned long timeout; u32 con; int do_send_init_stream = 0; @@ -1603,22 +1615,7 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) } } - omap_hsmmc_stop_clock(host); - - regval = OMAP_HSMMC_READ(host->base, SYSCTL); - regval = regval & ~(CLKD_MASK); - regval = regval | (calc_divisor(ios) << 6) | (DTO << 16); - OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); - OMAP_HSMMC_WRITE(host->base, SYSCTL, - OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); - - /* Wait till the ICS bit is set */ - timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); - while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS - && time_before(jiffies, timeout)) - msleep(1); - - omap_hsmmc_start_clock(host); + omap_hsmmc_set_clock(host); if (do_send_init_stream) send_init_stream(host);