From patchwork Fri May 13 05:47:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arindam Nath X-Patchwork-Id: 781742 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p4D5m2jh009499 for ; Fri, 13 May 2011 05:48:31 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756270Ab1EMFsa (ORCPT ); Fri, 13 May 2011 01:48:30 -0400 Received: from mail-px0-f173.google.com ([209.85.212.173]:44399 "EHLO mail-px0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756064Ab1EMFsa (ORCPT ); Fri, 13 May 2011 01:48:30 -0400 Received: by pxi16 with SMTP id 16so1480154pxi.4 for ; Thu, 12 May 2011 22:48:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:cc:subject:date:message-id :x-mailer:in-reply-to:references; bh=5BWl3y4r+cM/Y9F5bp5urBbJ6i6Xjy7lL/F9MNP95bQ=; b=Hzgn7u7yMZX1AQbQZ5edaZVpUvGNidLGT3qzgldugmVVhJgKNgAc+wVbDNtws+6ZX4 7ttekm2hg6FaSbifECok/ER32PADuHZbvquy78hYPanKJUlAZmc7FZd+GGLZPF5hIplg IfSVmodwJ+9hg6A+fN3NECyJeKCvAHiQLZ/zg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; b=EdkOBDFp2k2jqJIkh+tawXFCXe8YB+K+Btp8Yr+aXsWXdlRiZ4HXtMGeJeTCJjZtEn WgLE7Zi2vHAzqj7Zm04ViolDU0ivsDFRV9i93abo3FPIYyMNpP5/HLfcm9mdmIIIn0Jm sGomRwhXJb5x1eU8+cO6rqKHYS+FaKvanXNJE= Received: by 10.68.5.164 with SMTP id t4mr1623539pbt.167.1305265709877; Thu, 12 May 2011 22:48:29 -0700 (PDT) Received: from localhost ([122.167.11.185]) by mx.google.com with ESMTPS id e2sm1143966pbf.47.2011.05.12.22.48.24 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 12 May 2011 22:48:29 -0700 (PDT) From: Arindam Nath To: cjb@laptop.org Cc: linux-mmc@vger.kernel.org, prakity@marvell.com, zhangfei.gao@gmail.com, Arindam Nath Subject: [PATCH v2 2/4] sdhci pxa add platform specific code for UHS signaling Date: Fri, 13 May 2011 11:17:16 +0530 Message-Id: <1305265638-1572-3-git-send-email-arindam.nath@amd.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1305265638-1572-1-git-send-email-arindam.nath@amd.com> References: <1305265638-1572-1-git-send-email-arindam.nath@amd.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 13 May 2011 05:48:31 +0000 (UTC) From: Philip Rakity Marvell controller requires 1.8V bit in UHS control register 2 be set when doing UHS. eMMC does not require 1.8V for DDR. add platform code to handle this. Signed-off-by: Philip Rakity Reviewed-by: Arindam Nath --- drivers/mmc/host/sdhci-pxa.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 files changed, 41 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/host/sdhci-pxa.c b/drivers/mmc/host/sdhci-pxa.c index 5a61208..1dc9deb 100644 --- a/drivers/mmc/host/sdhci-pxa.c +++ b/drivers/mmc/host/sdhci-pxa.c @@ -69,7 +69,45 @@ static void set_clock(struct sdhci_host *host, unsigned int clock) } } +static int set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) +{ + u16 ctrl_2; + + /* + * Set V18_EN -- UHS modes do not work without this. + * does not change signaling voltage + */ + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + switch (uhs) { + case MMC_TIMING_UHS_SDR12: + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; + break; + case MMC_TIMING_UHS_SDR25: + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; + break; + case MMC_TIMING_UHS_SDR50: + ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180; + break; + case MMC_TIMING_UHS_SDR104: + ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; + break; + case MMC_TIMING_UHS_DDR50: + ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; + break; + } + + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + pr_debug("%s:%s uhs = %d, ctrl_2 = %04X\n", + __func__, mmc_hostname(host->mmc), uhs, ctrl_2); + + return 0; +} + static struct sdhci_ops sdhci_pxa_ops = { + .set_uhs_signaling = set_uhs_signaling, .set_clock = set_clock, }; @@ -141,6 +179,9 @@ static int __devinit sdhci_pxa_probe(struct platform_device *pdev) if (pdata->quirks) host->quirks |= pdata->quirks; + /* enable 1/8V DDR capable */ + host->mmc->caps |= MMC_CAP_1_8V_DDR; + /* If slot design supports 8 bit data, indicate this to MMC. */ if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) host->mmc->caps |= MMC_CAP_8_BIT_DATA;