From patchwork Fri Sep 28 07:56:11 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 1517551 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 469D03FC71 for ; Fri, 28 Sep 2012 08:02:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756569Ab2I1ICL (ORCPT ); Fri, 28 Sep 2012 04:02:11 -0400 Received: from na3sys009aog134.obsmtp.com ([74.125.149.83]:56648 "EHLO na3sys009aog134.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756685Ab2I1ICJ (ORCPT ); Fri, 28 Sep 2012 04:02:09 -0400 Received: from MSI-MTA.marvell.com ([65.219.4.132]) (using TLSv1) by na3sys009aob134.postini.com ([74.125.148.12]) with SMTP ID DSNKUGVZfLJ184YrdWdrcvAwmrv2sKOy4udQ@postini.com; Fri, 28 Sep 2012 01:02:09 PDT Received: from maili.marvell.com ([10.68.76.210]) by MSI-MTA.marvell.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 28 Sep 2012 01:01:42 -0700 Received: from localhost.localdomain (unknown [10.38.36.240]) by maili.marvell.com (Postfix) with ESMTP id 327FA4E510; Fri, 28 Sep 2012 01:01:41 -0700 (PDT) From: Kevin Liu To: linux-mmc@vger.kernel.org, cjb@laptop.org, pierre@ossman.eu, ulf.hansson@linaro.org, zgao6@marvell.com Cc: hzhuang1@marvell.com, cxie4@marvell.com, prakity@marvell.com, kliu5@marvell.com Subject: [PATCH v5 12/13] mmc: sdhci: fix the bug that DDR50 can't work for emmc Date: Fri, 28 Sep 2012 15:56:11 +0800 Message-Id: <1348818972-26711-13-git-send-email-keyuan.liu@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1348818972-26711-1-git-send-email-keyuan.liu@gmail.com> References: <1348818972-26711-1-git-send-email-keyuan.liu@gmail.com> X-OriginalArrivalTime: 28 Sep 2012 08:01:42.0440 (UTC) FILETIME=[7F201A80:01CD9D4F] Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Kevin Liu Host controller must enable 1.8v signal for UHS modes. Otherwise UHS modes won't take effect. But mmc core does NOT switch to 1.8v for DDR50 mode. So enable the 1.8v signal for mmc DDR50 mode in host driver. In JEDEC spec, there are two emmc device types which support DDR50. One type can work under signal 1.2v while the other type work under signal 1.8v or 3v. So current code just keep 3v for the second device type. But in SD host spec, 1.8v signal must be enabled for all UHS modes taking effect. So the fact is, if using SD host to work with emmc chip, then 1.8v signal must be selected in order to enable DDR50. Current code missed this. Because DDR50 shall can work under both signal 1.8v and 3v according to JEDEC spec, So should not switch to 1.8v in mmc core code. It's the host controller requirement that 1.8v signal must be enabled in order to enable DDR50, which conflict with emmc spec. So add this in host driver. Signed-off-by: Kevin Liu --- drivers/mmc/host/sdhci.c | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 1faa5ec..fbf94b0 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1529,8 +1529,15 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) ctrl_2 |= SDHCI_CTRL_UHS_SDR50; else if (ios->timing == MMC_TIMING_UHS_SDR104) ctrl_2 |= SDHCI_CTRL_UHS_SDR104; - else if (ios->timing == MMC_TIMING_UHS_DDR50) + else if (ios->timing == MMC_TIMING_UHS_DDR50) { + struct mmc_card *card; + ctrl_2 |= SDHCI_CTRL_UHS_DDR50; + card = container_of(&(host->mmc), + struct mmc_card, host); + if (mmc_card_mmc(card)) + ctrl_2 |= SDHCI_CTRL_VDD_180; + } sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); } if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&