From patchwork Wed Oct 17 11:04:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 1604831 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id A8C6DDFABE for ; Wed, 17 Oct 2012 11:05:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756539Ab2JQLFZ (ORCPT ); Wed, 17 Oct 2012 07:05:25 -0400 Received: from na3sys009aog103.obsmtp.com ([74.125.149.71]:54626 "EHLO na3sys009aog103.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756300Ab2JQLFY (ORCPT ); Wed, 17 Oct 2012 07:05:24 -0400 Received: from MSI-MTA.marvell.com ([65.219.4.132]) (using TLSv1) by na3sys009aob103.postini.com ([74.125.148.12]) with SMTP ID DSNKUH6Q8FSRBqDEVriV9+sf7XE9IcbPX/nG@postini.com; Wed, 17 Oct 2012 04:05:24 PDT Received: from maili.marvell.com ([10.68.76.210]) by MSI-MTA.marvell.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 17 Oct 2012 04:05:02 -0700 Received: from localhost.localdomain (unknown [10.38.36.240]) by maili.marvell.com (Postfix) with ESMTP id 0C7FB4E510; Wed, 17 Oct 2012 04:05:00 -0700 (PDT) From: Kevin Liu To: linux-mmc@vger.kernel.org, cjb@laptop.org, pierre@ossman.eu, ulf.hansson@linaro.org, zgao6@marvell.com Cc: hzhuang1@marvell.com, cxie4@marvell.com, prakity@marvell.com, kliu5@marvell.com Subject: [PATCH v6 06/14] mmc: sdhci-pxav3: controller can't get base clock Date: Wed, 17 Oct 2012 19:04:45 +0800 Message-Id: <1350471893-29633-7-git-send-email-keyuan.liu@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1350471893-29633-1-git-send-email-keyuan.liu@gmail.com> References: <1350471893-29633-1-git-send-email-keyuan.liu@gmail.com> X-OriginalArrivalTime: 17 Oct 2012 11:05:02.0545 (UTC) FILETIME=[418C2C10:01CDAC57] Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Kevin Liu Enable the quirk SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN since SD_CAPABILITIES_1[15:8](BASE_FREQ) can't get correct base clock value. It return a fixed pre-set value like 200 on some sdhci-pxav3 based platforms like MMP3 while return 0 on the other sdhci-pxav3 based platforms. So we enable the quirk and get the base clock via function get_max_clock. Also add get_max_clock. Reported-by: Philip Rakity Reviewed-by: Philip Rakity Acked-by: Zhangfei Gao Signed-off-by: Kevin Liu --- drivers/mmc/host/sdhci-pxav3.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index e918a2b..ccd1906 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -163,10 +163,18 @@ static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) return 0; } +static u32 pxav3_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + + return clk_get_rate(pltfm_host->clk); +} + static struct sdhci_ops pxav3_sdhci_ops = { .platform_reset_exit = pxav3_set_private_registers, .set_uhs_signaling = pxav3_set_uhs_signaling, .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, + .get_max_clock = pxav3_get_max_clock, }; #ifdef CONFIG_OF @@ -249,7 +257,8 @@ static int __devinit sdhci_pxav3_probe(struct platform_device *pdev) host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC - | SDHCI_QUIRK_32BIT_ADMA_SIZE; + | SDHCI_QUIRK_32BIT_ADMA_SIZE + | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; /* enable 1/8V DDR capable */ host->mmc->caps |= MMC_CAP_1_8V_DDR;