From patchwork Fri Oct 19 02:51:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Porter X-Patchwork-Id: 1614831 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id F197740ADA for ; Fri, 19 Oct 2012 02:50:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964880Ab2JSCuu (ORCPT ); Thu, 18 Oct 2012 22:50:50 -0400 Received: from mail-ie0-f174.google.com ([209.85.223.174]:41901 "EHLO mail-ie0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932555Ab2JSCuQ (ORCPT ); Thu, 18 Oct 2012 22:50:16 -0400 Received: by mail-ie0-f174.google.com with SMTP id k13so7560iea.19 for ; Thu, 18 Oct 2012 19:50:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=l3OpBeHLz5k8zzVNVsGA5pWv6V3BwjczocJn0s2ju2A=; b=YRjmFJda8zO16aCLBbtcDEDcFkzsr/eu9YT3rZAAGHpD82XWuLb6oCZWX37tf5XFdt +NwMDi2gdF7ouzeaVfumUlOkXJv+D9YX4Xc0FSkZTZFdAW32foTnzVHbL4ZDC+E74ziI 9Vesl3T/+GYmy4S6SCPsQNdPBJxyHGq1KNeylmyBuoTZ6J4FDLevTa8er8MiAeyflJzt Ie9AWGQUp5Fipa+2mcnUqE4eoMF4ym9ArEd9GB5MJvZbLAuuGhow3osnHTIOeWq9HWIV N9qvDUIfqMFaMVsTOKK98Nc80SnPtO8XSM+GZ3rERzngufds49s32sZZnal1bAq/tDkE SSrg== Received: by 10.50.185.194 with SMTP id fe2mr7028918igc.60.1350615015568; Thu, 18 Oct 2012 19:50:15 -0700 (PDT) Received: from beef.ohporter.com (cpe-24-166-64-7.neo.res.rr.com. [24.166.64.7]) by mx.google.com with ESMTPS id rd10sm5461208igb.1.2012.10.18.19.50.14 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Oct 2012 19:50:14 -0700 (PDT) From: Matt Porter To: Vinod Koul Cc: Dan Williams , Chris Ball , Linux DaVinci Kernel List , Linux Kernel Mailing List , Linux MMC List Subject: [RFC PATCH 2/3] dma: edma: add device_channel_caps() support Date: Thu, 18 Oct 2012 22:51:27 -0400 Message-Id: <1350615088-14562-3-git-send-email-mporter@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1350615088-14562-1-git-send-email-mporter@ti.com> References: <1350615088-14562-1-git-send-email-mporter@ti.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Implement device_channel_caps(). EDMA has a finite set of PaRAM slots available for linking a multi-segment SG transfer. In order to prevent any one channel from consuming all PaRAM slots to fulfill a large SG transfer, the driver reports a static per-channel max number of SG segments it will handle. The maximum size of SG segment is limited by the slave config maxburst and addr_width for the channel in question. These values are used from the current channel config to calculate and return the max segment length cap. Signed-off-by: Matt Porter --- drivers/dma/edma.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 47ba7bf..8b41045 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -70,6 +70,7 @@ struct edma_chan { bool alloced; int slot[EDMA_MAX_SLOTS]; struct dma_slave_config cfg; + struct dmaengine_chan_caps caps; }; struct edma_cc { @@ -462,6 +463,28 @@ static void edma_issue_pending(struct dma_chan *chan) spin_unlock_irqrestore(&echan->vchan.lock, flags); } +static struct dmaengine_chan_caps +*edma_get_channel_caps(struct dma_chan *chan, enum dma_transfer_direction dir) +{ + struct edma_chan *echan; + enum dma_slave_buswidth width = 0; + u32 burst = 0; + + if (chan) { + echan = to_edma_chan(chan); + if (dir == DMA_MEM_TO_DEV) { + width = echan->cfg.dst_addr_width; + burst = echan->cfg.dst_maxburst; + } else if (dir == DMA_DEV_TO_MEM) { + width = echan->cfg.src_addr_width; + burst = echan->cfg.src_maxburst; + } + echan->caps.seg_len = (SZ_64K - 1) * width * burst; + return &echan->caps; + } + return NULL; +} + static size_t edma_desc_size(struct edma_desc *edesc) { int i; @@ -521,6 +544,8 @@ static void __init edma_chan_init(struct edma_cc *ecc, echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i); echan->ecc = ecc; echan->vchan.desc_free = edma_desc_free; + echan->caps.ops = DMAENGINE_SLAVE | DMAENGINE_SG; + echan->caps.seg_nr = MAX_NR_SG; vchan_init(&echan->vchan, dma); @@ -537,6 +562,7 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, dma->device_alloc_chan_resources = edma_alloc_chan_resources; dma->device_free_chan_resources = edma_free_chan_resources; dma->device_issue_pending = edma_issue_pending; + dma->device_channel_caps = edma_get_channel_caps; dma->device_tx_status = edma_tx_status; dma->device_control = edma_control; dma->dev = dev;