From patchwork Mon Feb 4 19:47:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Porter X-Patchwork-Id: 2094761 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 376263FD56 for ; Mon, 4 Feb 2013 19:46:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754517Ab3BDTqd (ORCPT ); Mon, 4 Feb 2013 14:46:33 -0500 Received: from mail-ie0-f172.google.com ([209.85.223.172]:52265 "EHLO mail-ie0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754141Ab3BDTq3 (ORCPT ); Mon, 4 Feb 2013 14:46:29 -0500 Received: by mail-ie0-f172.google.com with SMTP id c10so6308613ieb.31 for ; Mon, 04 Feb 2013 11:46:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=i7Hod9gtX2iDpcQ5DX3nn9xOZ7xzPzj6P4Jealf8UPM=; b=cOHWsXSUK3h/i4n6aDEHLkQhsyMwIlyMFh714mTfzKmqzfGcVCpwU1GPt2UzW5Adlx byKhl9Bvt2szjE11QQmpFufMoKHnofmLRj704GBcCOYYYDf+fg4bVcfWoadWFhuP1VTr 9Fdz+H6fFBe548ACLJ76ho85P8DebIpQvSUbE5Ofg6MHXT5D+a4afHGh/XzBmLr3PVpk 0Ocu6j6fhSBgpkr3KSXwIG0F+D3t+qU6btol92zaT7oNO8M7I0xXFBxzYpsRK957XFbR 4vu/pfdUkfzeJYjzVX8fw0vMwXl9256usTISYX70yhaMeafOeMjqZkHF8JR4u1HstgT4 U7yg== X-Received: by 10.50.45.166 with SMTP id o6mr8602135igm.0.1360007188744; Mon, 04 Feb 2013 11:46:28 -0800 (PST) Received: from beef.ohporter.com (cpe-24-166-64-7.neo.res.rr.com. [24.166.64.7]) by mx.google.com with ESMTPS id ww6sm16414630igb.2.2013.02.04.11.46.27 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 04 Feb 2013 11:46:28 -0800 (PST) From: Matt Porter To: Vinod Koul Cc: Dan Williams , Chris Ball , Grant Likely , Linux DaVinci Kernel List , Linux Kernel Mailing List , Linux MMC List Subject: [PATCH v3 3/3] mmc: davinci: get SG segment limits with dma_get_slave_sg_caps() Date: Mon, 4 Feb 2013 14:47:04 -0500 Message-Id: <1360007224-21735-4-git-send-email-mporter@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360007224-21735-1-git-send-email-mporter@ti.com> References: <1360007224-21735-1-git-send-email-mporter@ti.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Replace the hardcoded values used to set max_segs/max_seg_size with a dma_get_slave_sg_caps() query to the dmaengine driver. Signed-off-by: Matt Porter --- drivers/mmc/host/davinci_mmc.c | 37 ++++++++--------------------- include/linux/platform_data/mmc-davinci.h | 3 --- 2 files changed, 10 insertions(+), 30 deletions(-) diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c index 2063677..583cbd0 100644 --- a/drivers/mmc/host/davinci_mmc.c +++ b/drivers/mmc/host/davinci_mmc.c @@ -144,18 +144,6 @@ /* MMCSD Init clock in Hz in opendrain mode */ #define MMCSD_INIT_CLOCK 200000 -/* - * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, - * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only - * for drivers with max_segs == 1, making the segments bigger (64KB) - * than the page or two that's otherwise typical. nr_sg (passed from - * platform data) == 16 gives at least the same throughput boost, using - * EDMA transfer linkage instead of spending CPU time copying pages. - */ -#define MAX_CCNT ((1 << 16) - 1) - -#define MAX_NR_SG 16 - static unsigned rw_threshold = 32; module_param(rw_threshold, uint, S_IRUGO); MODULE_PARM_DESC(rw_threshold, @@ -216,8 +204,6 @@ struct mmc_davinci_host { u8 version; /* for ns in one cycle calculation */ unsigned ns_in_one_cycle; - /* Number of sg segments */ - u8 nr_sg; #ifdef CONFIG_CPU_FREQ struct notifier_block freq_transition; #endif @@ -1165,6 +1151,7 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev) struct resource *r, *mem = NULL; int ret = 0, irq = 0; size_t mem_size; + struct dma_slave_sg_caps *dma_sg_caps; /* REVISIT: when we're fully converted, fail if pdata is NULL */ @@ -1214,12 +1201,6 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev) init_mmcsd_host(host); - if (pdata->nr_sg) - host->nr_sg = pdata->nr_sg - 1; - - if (host->nr_sg > MAX_NR_SG || !host->nr_sg) - host->nr_sg = MAX_NR_SG; - host->use_dma = use_dma; host->mmc_irq = irq; host->sdio_irq = platform_get_irq(pdev, 1); @@ -1248,14 +1229,16 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev) mmc->caps |= pdata->caps; mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; - /* With no iommu coalescing pages, each phys_seg is a hw_seg. - * Each hw_seg uses one EDMA parameter RAM slot, always one - * channel and then usually some linked slots. - */ - mmc->max_segs = MAX_NR_SG; + /* Just check one channel for the DMA SG limits */ + dma_sg_caps = dma_get_slave_sg_caps( + host->dma_tx, + DMA_SLAVE_BUSWIDTH_4_BYTES, + rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES); - /* EDMA limit per hw segment (one or two MBytes) */ - mmc->max_seg_size = MAX_CCNT * rw_threshold; + if (dma_sg_caps) { + mmc->max_segs = dma_sg_caps->max_seg_nr; + mmc->max_seg_size = dma_sg_caps->max_seg_len; + } /* MMC/SD controller limits for multiblock requests */ mmc->max_blk_size = 4095; /* BLEN is 12 bits */ diff --git a/include/linux/platform_data/mmc-davinci.h b/include/linux/platform_data/mmc-davinci.h index 5ba6b22..6910209 100644 --- a/include/linux/platform_data/mmc-davinci.h +++ b/include/linux/platform_data/mmc-davinci.h @@ -25,9 +25,6 @@ struct davinci_mmc_config { /* Version of the MMC/SD controller */ u8 version; - - /* Number of sg segments */ - u8 nr_sg; }; void davinci_setup_mmc(int module, struct davinci_mmc_config *config);