From patchwork Wed Mar 6 19:56:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Porter X-Patchwork-Id: 2228051 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id CB548DFABD for ; Wed, 6 Mar 2013 19:56:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754561Ab3CFT4Q (ORCPT ); Wed, 6 Mar 2013 14:56:16 -0500 Received: from mail-ie0-f182.google.com ([209.85.223.182]:52198 "EHLO mail-ie0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754578Ab3CFTzl (ORCPT ); Wed, 6 Mar 2013 14:55:41 -0500 Received: by mail-ie0-f182.google.com with SMTP id k14so10012943iea.13 for ; Wed, 06 Mar 2013 11:55:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=5PCmjKNfxbgd8DYizZv5TvyzS/N5N6Z3kMhxClFAQSQ=; b=EwSiRpGDYD6aT04Lhp1F206aTJebIpzeiiwXVWMPWimmz63IpaQcouy9q1+DGuj+6u WJm48YxmKouar/CxyakNABbtiZTmH7VWDx+9DyCMO/j4j9DSeooF8loYb7kzg+NNDpRB rOfINKcYzBskqfMzPKYbc6uwlFUMYNTz+V0L3N3qIzXv3iMGacjPQP1Tys3ZBIkSz64Q +tSGO2Pc6RHN7XhCHjxysLTwnoYt5WWe+nGThieh94pa9bAI3L3A4OcdLsn0Ls3jD3bm Fy3ps7VhPgoJEYH/V/YqH8X+EaWfGODiJbMOE8YEFO0khaCDAsZhOlTMgq5dYs1cCq4h NVxw== X-Received: by 10.50.1.198 with SMTP id 6mr11803891igo.0.1362599740602; Wed, 06 Mar 2013 11:55:40 -0800 (PST) Received: from beef.ohporter.com (cpe-98-27-254-98.neo.res.rr.com. [98.27.254.98]) by mx.google.com with ESMTPS id wx2sm25991191igb.4.2013.03.06.11.55.39 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 06 Mar 2013 11:55:40 -0800 (PST) From: Matt Porter To: Vinod Koul , Chris Ball Cc: Dan Williams , Sekhar Nori , Grant Likely , Linux DaVinci Kernel List , Linux Kernel Mailing List , Linux MMC List Subject: [PATCH v4 1/3] dmaengine: add dma_get_slave_sg_limits() Date: Wed, 6 Mar 2013 14:56:05 -0500 Message-Id: <1362599767-11292-2-git-send-email-mporter@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1362599767-11292-1-git-send-email-mporter@ti.com> References: <1362599767-11292-1-git-send-email-mporter@ti.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add a dmaengine API to retrieve slave SG transfer limits. The API is optionally implemented by dmaengine drivers and when unimplemented will return a NULL pointer. A client driver using this API provides the required dma channel, address width, and burst size of the transfer. dma_get_slave_sg_limits() returns an SG limits structure with the maximum number and size of SG segments that the given channel can handle. Signed-off-by: Matt Porter --- include/linux/dmaengine.h | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 91ac8da..a4a6aac 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -371,6 +371,18 @@ struct dma_slave_config { unsigned int slave_id; }; +/* struct dma_slave_sg_limits - expose SG transfer limits of a channel + * + * @max_seg_nr: maximum number of SG segments supported on a SG/SLAVE + * channel (0 for no maximum or not a SG/SLAVE channel) + * @max_seg_len: maximum length of SG segments supported on a SG/SLAVE + * channel (0 for no maximum or not a SG/SLAVE channel) + */ +struct dma_slave_sg_limits { + u32 max_seg_nr; + u32 max_seg_len; +}; + static inline const char *dma_chan_name(struct dma_chan *chan) { return dev_name(&chan->dev->device); @@ -534,6 +546,7 @@ struct dma_tx_state { * struct with auxiliary transfer status information, otherwise the call * will just return a simple status code * @device_issue_pending: push pending transactions to hardware + * @device_slave_sg_limits: return the slave SG capabilities */ struct dma_device { @@ -602,6 +615,9 @@ struct dma_device { dma_cookie_t cookie, struct dma_tx_state *txstate); void (*device_issue_pending)(struct dma_chan *chan); + struct dma_slave_sg_limits *(*device_slave_sg_limits)( + struct dma_chan *chan, enum dma_slave_buswidth addr_width, + u32 maxburst); }; static inline int dmaengine_device_control(struct dma_chan *chan, @@ -963,6 +979,29 @@ dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, } } +/** + * dma_get_slave_sg_limits - get DMAC SG transfer capabilities + * @chan: target DMA channel + * @addr_width: address width of the DMA transfer + * @maxburst: maximum DMA transfer burst size + * + * Get SG transfer capabilities for a specified channel. If the dmaengine + * driver does not implement SG transfer capabilities then NULL is + * returned. + */ +static inline struct dma_slave_sg_limits +*dma_get_slave_sg_limits(struct dma_chan *chan, + enum dma_slave_buswidth addr_width, + u32 maxburst) +{ + if (chan->device->device_slave_sg_limits) + return chan->device->device_slave_sg_limits(chan, + addr_width, + maxburst); + + return NULL; +} + enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); #ifdef CONFIG_DMA_ENGINE enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);