@@ -2244,6 +2244,16 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
SDHCI_INT_INDEX))
host->cmd->error = -EILSEQ;
+ if (host->quirks2 & SDHCI_QUIRK2_IGNORE_CMDCRC_FOR_TUNING) {
+ if ((host->cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) ||
+ (host->cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
+ if (intmask & SDHCI_INT_CRC) {
+ sdhci_reset(host, SDHCI_RESET_CMD);
+ host->cmd->error = 0;
+ }
+ }
+ }
+
if (host->cmd->error) {
tasklet_schedule(&host->finish_tasklet);
return;
@@ -2271,6 +2281,16 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
* fall through and take the SDHCI_INT_RESPONSE */
}
+ if (host->quirks2 & SDHCI_QUIRK2_IGNORE_CMDCRC_FOR_TUNING) {
+ if ((host->cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) ||
+ (host->cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
+ if (intmask & SDHCI_INT_CRC) {
+ sdhci_finish_command(host);
+ return;
+ }
+ }
+ }
+
if (intmask & SDHCI_INT_RESPONSE)
sdhci_finish_command(host);
}
@@ -102,6 +102,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_RDWR_TX_ACTIVE_EOT (1<<6)
/* Controller clears interrupt slowly and IRQ handler may be called twice */
#define SDHCI_QUIRK2_SLOW_INT_CLR (1<<7)
+/* Ignore CMD CRC errors for tuning commands */
+#define SDHCI_QUIRK2_IGNORE_CMDCRC_FOR_TUNING (1<<8)
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
The Qualcomm MSM SDHCI controller doesn't support tuning as specified by the Standard Host Controller 3.0 spec. As a result of which, CMD CRC errors are expected for tuning commands. Hence, add a new quirk SDHCI_QUIRK2_IGNORE_CMDCRC_FOR_TUNING to ignore those errors for tuning commands. CC: Sahitya Tummala <stummala@codeaurora.org> Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> --- drivers/mmc/host/sdhci.c | 20 ++++++++++++++++++++ include/linux/mmc/sdhci.h | 2 ++ 2 files changed, 22 insertions(+)