From patchwork Fri Aug 16 11:55:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuvaraj CD X-Patchwork-Id: 2845620 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B6DDD9F271 for ; Fri, 16 Aug 2013 11:55:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 93B9320205 for ; Fri, 16 Aug 2013 11:55:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7EF85201FB for ; Fri, 16 Aug 2013 11:55:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754537Ab3HPLzv (ORCPT ); Fri, 16 Aug 2013 07:55:51 -0400 Received: from mail-pd0-f178.google.com ([209.85.192.178]:38807 "EHLO mail-pd0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754417Ab3HPLzv (ORCPT ); Fri, 16 Aug 2013 07:55:51 -0400 Received: by mail-pd0-f178.google.com with SMTP id w10so2143202pde.23 for ; Fri, 16 Aug 2013 04:55:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TEL9ky2q4TJoDCs4xP1ln0JHJ+TDF2d/Uo9HWP7XP9w=; b=0uWB+uMm1zgWSBkPkp05YFtGcym/Aqo7T17Qolt6cIwI9zUn4T6uWuvymxV7a1VAAJ kDZrmTEli9wOy7txWZXFRk4MymtWZJjSEKsHbVHyKScmn13+4qkb9A0KKee/vj90X9DL cSlc6MpRUVWXPsLwPDheyqDn6AQoqd1vMzuTmDFbVG3djY3S67NkzO0QyVw3Gn/SaoCM StSEu6/oefOI+iUVOihV0GQhCjnvVywTWvQuxVlwi7taGuXQcQNL0a/chz702zNJ+GPN JPgEaN652+t4bi8FmDc1NDP9opHrWi28aOydwpafH27h1bD/SnchvIP/sgTefp6p1CP/ MZsQ== X-Received: by 10.66.221.8 with SMTP id qa8mr679556pac.188.1376654150593; Fri, 16 Aug 2013 04:55:50 -0700 (PDT) Received: from yuvaraj-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id pw9sm1734598pbb.20.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 16 Aug 2013 04:55:50 -0700 (PDT) From: Yuvaraj Kumar C D To: cjb@laptop.org, jh80.chung@samsung.com, tgih.jun@samsung.com, linux-mmc@vger.kernel.org, thomas.ab@samsung.com Cc: Yuvaraj Kumar C D Subject: [RFC 3/3] mmc: dw_mmc: exynos: add a quirk for SMU. Date: Fri, 16 Aug 2013 17:25:09 +0530 Message-Id: <1376654109-32119-3-git-send-email-yuvaraj.cd@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1376654109-32119-1-git-send-email-yuvaraj.cd@samsung.com> References: <1376654109-32119-1-git-send-email-yuvaraj.cd@samsung.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Exynos5420 Mobile Storage Host controller has Security Management Unit (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch adds a quirk to bypass SMU as it is not being used yet. This patch is on top of the below patch by Doug Anderson. mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT Signed-off-by: Yuvaraj Kumar C D --- drivers/mmc/host/dw_mmc-exynos.c | 41 ++++++++++++++++++++++++++++++++++++++ drivers/mmc/host/dw_mmc.c | 3 +++ include/linux/mmc/dw_mmc.h | 2 ++ 3 files changed, 46 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 19c845b..5d82c45 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -35,6 +35,25 @@ #define EXYNOS4210_FIXED_CIU_CLK_DIV 2 #define EXYNOS4412_FIXED_CIU_CLK_DIV 4 +/* Block number in eMMC */ +#define DWMCI_BLOCK_NUM 0xFFFFFFFF + +#define SDMMC_EMMCP_BASE 0x1000 +#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010) +#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200) +#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204) +#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C) + +/* SMU control bits */ +#define DWMCI_MPSCTRL_SECURE_READ_BIT BIT(7) +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6) +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT BIT(5) +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) +#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3) +#define DWMCI_MPSCTRL_ECB_MODE BIT(2) +#define DWMCI_MPSCTRL_ENCRYPTION BIT(1) +#define DWMCI_MPSCTRL_VALID BIT(0) + /* Variations in Exynos specific dw-mshc controller */ enum dw_mci_exynos_type { DW_MCI_TYPE_EXYNOS4210, @@ -74,6 +93,17 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) { struct dw_mci_exynos_priv_data *priv = host->priv; + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420 && + host->pdata->quirks & DW_MCI_QUIRK_BYPASS_SMU) { + mci_writel(host, MPSBEGIN0, 0); + mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM); + mci_writel(host, MPSCTRL0, + DWMCI_MPSCTRL_SECURE_WRITE_BIT | + DWMCI_MPSCTRL_NON_SECURE_READ_BIT | + DWMCI_MPSCTRL_VALID | + DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT); + } + return 0; } @@ -106,7 +136,18 @@ static int dw_mci_exynos_suspend(struct device *dev) static int dw_mci_exynos_resume(struct device *dev) { struct dw_mci *host = dev_get_drvdata(dev); + struct dw_mci_exynos_priv_data *priv = host->priv; + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420 && + host->pdata->quirks & DW_MCI_QUIRK_BYPASS_SMU) { + mci_writel(host, MPSBEGIN0, 0); + mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM); + mci_writel(host, MPSCTRL0, + DWMCI_MPSCTRL_SECURE_WRITE_BIT | + DWMCI_MPSCTRL_NON_SECURE_READ_BIT | + DWMCI_MPSCTRL_VALID | + DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT); + } return dw_mci_resume(host); } diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 0c0cada..49df69f 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2107,6 +2107,9 @@ static struct dw_mci_of_quirks { }, { .quirk = "broken-cd", .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, + }, { + .quirk = "bypass-smu", + .id = DW_MCI_QUIRK_BYPASS_SMU, }, }; diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h index 198f0fa..2d3f83f 100644 --- a/include/linux/mmc/dw_mmc.h +++ b/include/linux/mmc/dw_mmc.h @@ -209,6 +209,8 @@ struct dw_mci_dma_ops { #define DW_MCI_QUIRK_HIGHSPEED BIT(2) /* Unreliable card detection */ #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3) +/*Bypass the Security management unit*/ +#define DW_MCI_QUIRK_BYPASS_SMU BIT(4) /* Slot level quirks */ /* This slot has no write protect */