From patchwork Wed Aug 21 06:35:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuvaraj CD X-Patchwork-Id: 2847507 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 57E9E9F239 for ; Wed, 21 Aug 2013 06:36:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0DB7D20134 for ; Wed, 21 Aug 2013 06:36:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 37FB020165 for ; Wed, 21 Aug 2013 06:36:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752461Ab3HUGgF (ORCPT ); Wed, 21 Aug 2013 02:36:05 -0400 Received: from mail-pa0-f54.google.com ([209.85.220.54]:33260 "EHLO mail-pa0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752309Ab3HUGgB (ORCPT ); Wed, 21 Aug 2013 02:36:01 -0400 Received: by mail-pa0-f54.google.com with SMTP id kx10so464363pab.41 for ; Tue, 20 Aug 2013 23:36:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=iXOtqn35wc+K3DyZEO1gL6z6aAzX+WVTdLPXCJh0WkA=; b=E4tMK8A6Ct6nY8rGlRD5SdfpN2NywmNZuVQul2CAfcte1cmV+5IDv7mDrQPgorcT8s 3Lcj8uFhEusR1hecYcMXP+L1Uo4Xt4nL6RMV21+m6a2wi5sXc6xvccwykdceWM9C8GYF MiqkJh/IeVA2sCwnFRohvl7XUvkbrlQpJiuMDj4s6LyP+Z6tMiaprg/hf3YSkwQnPzbo T/kSDUlizbjRLUgVZSl9WBF22E0PUpQpYBlDrE3NIpHkeKWCtH8nuAE0cIZBRoyMRdIy 5gpTdORJfoZbWzff0cb9JqZ8INHWTVo0IHw48hApJOmEeUZ6HIo+AvLWYBOqUemXdpyY YrLQ== X-Received: by 10.68.252.194 with SMTP id zu2mr6099539pbc.58.1377066960452; Tue, 20 Aug 2013 23:36:00 -0700 (PDT) Received: from yuvaraj-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id ar5sm6288313pbc.40.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 20 Aug 2013 23:35:59 -0700 (PDT) From: Yuvaraj Kumar C D To: linux-samsung-soc@vger.kernel.org, linux-mmc@vger.kernel.org, kgene.kim@samsung.com Cc: ks.giri@samsung.com, Yuvaraj Kumar C D Subject: [PATCH V2] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC Date: Wed, 21 Aug 2013 12:05:32 +0530 Message-Id: <1377066933-28058-1-git-send-email-yuvaraj.cd@samsung.com> X-Mailer: git-send-email 1.7.9.5 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the device tree node entries for exynos5420 SOC. Exynos5420 has a different version of DWMMC controller,so a new compatible string is used to distinguish it from the prior SOC's. changes since V1: 1.disable node by status = disabled in SOC file 2.enable node by status = okay in board specific file Signed-off-by: Yuvaraj Kumar C D --- .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 + arch/arm/boot/dts/exynos5420-smdk5420.dts | 39 ++++++++++++++++++++ arch/arm/boot/dts/exynos5420.dtsi | 36 ++++++++++++++++++ 3 files changed, 77 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index 6d1c098..84cd56f 100644 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt @@ -16,6 +16,8 @@ Required Properties: specific extensions. - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 specific extensions. + - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420 + specific extensions. * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface unit (ciu) clock. This property is applicable only for Exynos5 SoC's and diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 08607df..0b2e464 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -30,4 +30,43 @@ clock-frequency = <24000000>; }; }; + + dwmmc0@12200000 { + status = "okay"; + num-slots = <1>; + broken-cd; + bypass-smu; + supports-highspeed; + fifo-depth = <0x80>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; + }; + + dwmmc2@12220000 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + fifo-depth = <0x80>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 9e90d1e..d9220c3 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -19,6 +19,9 @@ compatible = "samsung,exynos5420"; aliases { + mshc0 = &dwmmc_0; + mshc1 = &dwmmc_1; + mshc2 = &dwmmc_2; pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; @@ -65,6 +68,39 @@ #clock-cells = <1>; }; + dwmmc_0: dwmmc0@12200000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12200000 0x2000>; + clocks = <&clock 351>, <&clock 132>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + dwmmc_1: dwmmc1@12210000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12210000 0x2000>; + clocks = <&clock 352>, <&clock 133>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + dwmmc_2: dwmmc2@12220000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12220000 0x2000>; + clocks = <&clock 353>, <&clock 134>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>;