From patchwork Thu Oct 17 07:19:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 3059111 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 152BBBF924 for ; Thu, 17 Oct 2013 07:19:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B66A020398 for ; Thu, 17 Oct 2013 07:19:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7FCAA20176 for ; Thu, 17 Oct 2013 07:19:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751106Ab3JQHTE (ORCPT ); Thu, 17 Oct 2013 03:19:04 -0400 Received: from mail-db9lp0251.outbound.messaging.microsoft.com ([213.199.154.251]:8348 "EHLO db9outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751712Ab3JQHTD (ORCPT ); Thu, 17 Oct 2013 03:19:03 -0400 Received: from mail30-db9-R.bigfish.com (10.174.16.245) by DB9EHSOBE024.bigfish.com (10.174.14.87) with Microsoft SMTP Server id 14.1.225.22; Thu, 17 Oct 2013 07:19:01 +0000 Received: from mail30-db9 (localhost [127.0.0.1]) by mail30-db9-R.bigfish.com (Postfix) with ESMTP id DC7AC402A6; Thu, 17 Oct 2013 07:19:01 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275dh1de097hz2dh87h2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h1151h1155h) X-FB-DOMAIN-IP-MATCH: fail Received: from mail30-db9 (localhost.localdomain [127.0.0.1]) by mail30-db9 (MessageSwitch) id 1381994339731510_15677; Thu, 17 Oct 2013 07:18:59 +0000 (UTC) Received: from DB9EHSMHS029.bigfish.com (unknown [10.174.16.240]) by mail30-db9.bigfish.com (Postfix) with ESMTP id A46DA2A0062; Thu, 17 Oct 2013 07:18:59 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB9EHSMHS029.bigfish.com (10.174.14.39) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 17 Oct 2013 07:18:55 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.3.158.2; Thu, 17 Oct 2013 07:18:53 +0000 Received: from S2101-09.ap.freescale.net ([10.192.185.68]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r9H7IiBA012106; Thu, 17 Oct 2013 00:18:50 -0700 From: Shawn Guo To: CC: , Dong Aisheng , Chris Ball , , Shawn Guo Subject: [PATCH v2 2/4] mmc: sdhci-esdhc-imx: add flag ESDHC_FLAG_USDHC Date: Thu, 17 Oct 2013 15:19:45 +0800 Message-ID: <1381994387-9656-3-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1381994387-9656-1-git-send-email-shawn.guo@linaro.org> References: <1381994387-9656-1-git-send-email-shawn.guo@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add flag ESDHC_FLAG_USDHC to tell that the ESDHC is actually an USDHC block, and replace the is_imx6q_usdhc() occurrences with inline function esdhc_is_usdhc() which checks the flag. Signed-off-by: Shawn Guo --- drivers/mmc/host/sdhci-esdhc-imx.c | 37 ++++++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index d844be8..2421ac7 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -89,6 +89,11 @@ * affects i.MX25 and i.MX35. */ #define ESDHC_FLAG_ENGCM07207 BIT(2) +/* + * The flag tells that the ESDHC controller is an USDHC block that is + * integrated on the i.MX6 series. + */ +#define ESDHC_FLAG_USDHC BIT(3) enum imx_esdhc_type { IMX25_ESDHC, @@ -175,6 +180,11 @@ static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) return data->devtype == IMX6Q_USDHC; } +static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) +{ + return !!(data->flags & ESDHC_FLAG_USDHC); +} + static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) { void __iomem *base = host->ioaddr + (reg & ~0x3); @@ -213,11 +223,11 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) } } - if (unlikely(reg == SDHCI_CAPABILITIES_1) && is_imx6q_usdhc(imx_data)) + if (unlikely(reg == SDHCI_CAPABILITIES_1) && esdhc_is_usdhc(imx_data)) val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50; - if (unlikely(reg == SDHCI_MAX_CURRENT) && is_imx6q_usdhc(imx_data)) { + if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { val = 0; val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; @@ -307,7 +317,7 @@ static u16 esdhc_readw_le(struct sdhci_host *host, int reg) if (unlikely(reg == SDHCI_HOST_VERSION)) { reg ^= 2; - if (is_imx6q_usdhc(imx_data)) { + if (esdhc_is_usdhc(imx_data)) { /* * The usdhc register returns a wrong host version. * Correct it here. @@ -321,7 +331,7 @@ static u16 esdhc_readw_le(struct sdhci_host *host, int reg) if (val & ESDHC_VENDOR_SPEC_VSELECT) ret |= SDHCI_CTRL_VDD_180; - if (is_imx6q_usdhc(imx_data)) { + if (esdhc_is_usdhc(imx_data)) { val = readl(host->ioaddr + ESDHC_MIX_CTRL); if (val & ESDHC_MIX_CTRL_EXE_TUNE) ret |= SDHCI_CTRL_EXEC_TUNING; @@ -379,7 +389,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); } - if (is_imx6q_usdhc(imx_data)) { + if (esdhc_is_usdhc(imx_data)) { u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); /* Swap AC23 bit */ if (val & SDHCI_TRNS_AUTO_CMD23) { @@ -404,7 +414,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) imx_data->multiblock_status = MULTIBLK_IN_PROCESS; - if (is_imx6q_usdhc(imx_data)) + if (esdhc_is_usdhc(imx_data)) writel(val << 16, host->ioaddr + SDHCI_TRANSFER_MODE); else @@ -470,7 +480,7 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) * The reset on usdhc fails to clear MIX_CTRL register. * Do it manually here. */ - if (is_imx6q_usdhc(imx_data)) + if (esdhc_is_usdhc(imx_data)) writel(0, host->ioaddr + ESDHC_MIX_CTRL); } } @@ -507,7 +517,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, u32 temp, val; if (clock == 0) { - if (is_imx6q_usdhc(imx_data)) { + if (esdhc_is_usdhc(imx_data)) { val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, host->ioaddr + ESDHC_VENDOR_SPEC); @@ -515,7 +525,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, goto out; } - if (is_imx6q_usdhc(imx_data)) + if (esdhc_is_usdhc(imx_data)) pre_div = 1; temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); @@ -542,7 +552,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, | (pre_div << ESDHC_PREDIV_SHIFT)); sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); - if (is_imx6q_usdhc(imx_data)) { + if (esdhc_is_usdhc(imx_data)) { val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, host->ioaddr + ESDHC_VENDOR_SPEC); @@ -865,6 +875,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) imx_data->flags |= ESDHC_FLAG_ENGCM07207; + if (is_imx6q_usdhc(imx_data)) + imx_data->flags |= ESDHC_FLAG_USDHC; + imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); if (IS_ERR(imx_data->clk_ipg)) { err = PTR_ERR(imx_data->clk_ipg); @@ -917,7 +930,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) * The imx6q ROM code will change the default watermark level setting * to something insane. Change it back here. */ - if (is_imx6q_usdhc(imx_data)) + if (esdhc_is_usdhc(imx_data)) writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); boarddata = &imx_data->boarddata; @@ -980,7 +993,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) } /* sdr50 and sdr104 needs work on 1.8v signal voltage */ - if ((boarddata->support_vsel) && is_imx6q_usdhc(imx_data)) { + if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) { imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, ESDHC_PINCTRL_STATE_100MHZ); imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,