From patchwork Sat Nov 2 20:26:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Fenkart X-Patchwork-Id: 3131581 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 007219F244 for ; Sat, 2 Nov 2013 20:28:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D681C2031C for ; Sat, 2 Nov 2013 20:28:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B0DCB2031A for ; Sat, 2 Nov 2013 20:28:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753377Ab3KBU2e (ORCPT ); Sat, 2 Nov 2013 16:28:34 -0400 Received: from mail-ee0-f51.google.com ([74.125.83.51]:46700 "EHLO mail-ee0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751738Ab3KBU2c (ORCPT ); Sat, 2 Nov 2013 16:28:32 -0400 Received: by mail-ee0-f51.google.com with SMTP id t10so368611eei.24 for ; Sat, 02 Nov 2013 13:28:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=BwIFV0RVUn9mGg7cHu95JO51intD1TDdDLBOJo8Q2K8=; b=INzAcfihfa6eUngDSta0PSHFKuueSO13LZY9JVgXfGZ1gaLDez0IZPy73rce6+27QI 2DFNwO22C2kCq8WVUF5hkLAPW9Jkb52iEa+l6UgzQ/bS1SR11spI9eLJnZnRtLcPt7P6 rL2vtsHh9LkvBtK2Hvwh9g1lX/UKxyQfiiCX0SkkLVNQTGP7/c2H67pCAXqexbAzRJ5h KiZVpqrK4F2+e6jyuXWYMu3byBgiZ/ZrtJYCDVpoZQB3G++BsZOT6Sat1d8VyJr/bFSK SCRaTwuIwvf5eET53Yw3QWACFQAzkJCaw7481b4xnrk6N4CgugCHmWxcMgRfE63oGuuZ VeHw== X-Received: by 10.14.148.136 with SMTP id v8mr9047834eej.13.1383424110818; Sat, 02 Nov 2013 13:28:30 -0700 (PDT) Received: from localhost (ip-94-112-0-61.net.upcbroadband.cz. [94.112.0.61]) by mx.google.com with ESMTPSA id bn13sm24637586eeb.11.2013.11.02.13.28.28 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sat, 02 Nov 2013 13:28:30 -0700 (PDT) From: Andreas Fenkart To: Chris Ball Cc: Tony Lindgren , Grant Likely , Felipe Balbi , Balaji T K , zonque@gmail.com, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org, Andreas Fenkart , Andreas Fenkart Subject: [PATCH 1/3] mmc: omap_hsmmc: Enable SDIO IRQ. Date: Sat, 2 Nov 2013 21:26:14 +0100 Message-Id: <1383423976-24798-1-git-send-email-afenkart@gmail.com> X-Mailer: git-send-email 1.7.10.4 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Andreas Fenkart For now, only support SDIO interrupt if we are booted with DT. This is because some platforms need special quirks. And we don't want to add new legacy mux platform init code callbacks any longer as we are moving to DT based booting anyways. Broken hardware, missing the swakueup line, should fallback to polling, by setting 'ti,quirk-swakup-missing' in the device tree. Otherwise pending SDIO IRQ are not detected while in suspend. This affects am33xx processors. Reviewed-by: Grant Likely For the DT-Binding portion: Acked-by: Kumar Gala Signed-off-by: Andreas Fenkart --- .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 18 ++++ drivers/mmc/host/omap_hsmmc.c | 86 ++++++++++++++++++-- 2 files changed, 95 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt index ed271fc..1136e6b 100644 --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt @@ -20,6 +20,24 @@ ti,dual-volt: boolean, supports dual voltage cards ti,non-removable: non-removable slot (like eMMC) ti,needs-special-reset: Requires a special softreset sequence ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed +ti,quirk-swakup-missing: SOC missing the swakeup line, will not detect +SDIO irq while in suspend. Fallback to polling. Affected chips are +am335x, + + ------ + | PRCM | + ------ + ^ | + swakeup | | fclk + | v + ------ ------- ----- + | card | -- CIRQ --> | hsmmc | -- IRQ --> | CPU | + ------ ------- ----- + +In suspend the fclk is off and the module is disfunctional. Even +register reads will fail. A small logic in the host will request fclk +restore, when an external event is detected. Once the clock is +restored, the host detects the event normally. Example: mmc1: mmc@0x4809c000 { diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index b392130..6b0ec55 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -130,6 +130,7 @@ static void apply_clk_hack(struct device *dev) #define TC_EN (1 << 1) #define BWR_EN (1 << 4) #define BRR_EN (1 << 5) +#define CIRQ_EN (1 << 8) #define ERR_EN (1 << 15) #define CTO_EN (1 << 16) #define CCRC_EN (1 << 17) @@ -210,6 +211,9 @@ struct omap_hsmmc_host { int reqs_blocked; int use_reg; int req_in_progress; + int flags; +#define HSMMC_SDIO_IRQ_ENABLED (1 << 0) /* SDIO irq enabled */ + struct omap_hsmmc_next next_data; struct omap_mmc_platform_data *pdata; }; @@ -490,27 +494,40 @@ static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, struct mmc_command *cmd) { - unsigned int irq_mask; + u32 irq_mask = INT_EN_MASK; + unsigned long flags; if (host->use_dma) - irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN); - else - irq_mask = INT_EN_MASK; + irq_mask &= ~(BRR_EN | BWR_EN); /* Disable timeout for erases */ if (cmd->opcode == MMC_ERASE) irq_mask &= ~DTO_EN; + spin_lock_irqsave(&host->irq_lock, flags); OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); + + /* latch pending CIRQ, but don't signal */ + if (host->flags & HSMMC_SDIO_IRQ_ENABLED) + irq_mask |= CIRQ_EN; OMAP_HSMMC_WRITE(host->base, IE, irq_mask); + spin_unlock_irqrestore(&host->irq_lock, flags); } static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) { - OMAP_HSMMC_WRITE(host->base, ISE, 0); - OMAP_HSMMC_WRITE(host->base, IE, 0); + u32 irq_mask = 0; + unsigned long flags; + + spin_lock_irqsave(&host->irq_lock, flags); + /* no transfer running, need to signal cirq if enabled */ + if (host->flags & HSMMC_SDIO_IRQ_ENABLED) + irq_mask |= CIRQ_EN; + OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); + OMAP_HSMMC_WRITE(host->base, IE, irq_mask); OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); + spin_unlock_irqrestore(&host->irq_lock, flags); } /* Calculate divisor for the given clock frequency */ @@ -1067,8 +1084,12 @@ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) int status; status = OMAP_HSMMC_READ(host->base, STAT); - while (status & INT_EN_MASK && host->req_in_progress) { - omap_hsmmc_do_irq(host, status); + while (status & (INT_EN_MASK | CIRQ_EN)) { + if (host->req_in_progress) + omap_hsmmc_do_irq(host, status); + + if (status & CIRQ_EN) + mmc_signal_sdio_irq(host->mmc); /* Flush posted write */ status = OMAP_HSMMC_READ(host->base, STAT); @@ -1583,6 +1604,37 @@ static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) mmc_slot(host).init_card(card); } +static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) +{ + struct omap_hsmmc_host *host = mmc_priv(mmc); + u32 irq_mask; + unsigned long flags; + + spin_lock_irqsave(&host->irq_lock, flags); + + irq_mask = OMAP_HSMMC_READ(host->base, ISE); + if (enable) { + host->flags |= HSMMC_SDIO_IRQ_ENABLED; + irq_mask |= CIRQ_EN; + } else { + host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; + irq_mask &= ~CIRQ_EN; + } + OMAP_HSMMC_WRITE(host->base, IE, irq_mask); + + /* + * if enable, piggy back detection on current request + * but always disable immediately + */ + if (!host->req_in_progress || !enable) + OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); + + /* flush posted write */ + OMAP_HSMMC_READ(host->base, IE); + + spin_unlock_irqrestore(&host->irq_lock, flags); +} + static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) { u32 hctl, capa, value; @@ -1635,7 +1687,7 @@ static const struct mmc_host_ops omap_hsmmc_ops = { .get_cd = omap_hsmmc_get_cd, .get_ro = omap_hsmmc_get_ro, .init_card = omap_hsmmc_init_card, - /* NYET -- enable_sdio_irq */ + .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, }; #ifdef CONFIG_DEBUG_FS @@ -2021,6 +2073,22 @@ static int omap_hsmmc_probe(struct platform_device *pdev) dev_warn(&pdev->dev, "pins are not configured from the driver\n"); + /* + * For now, only support SDIO interrupt if we are booted with + * DT. This is because some platforms need special quirks. And + * we don't want to add new legacy mux platform init code + * callbacks any longer as we are moving to DT based booting + * anyways. + */ + if (pdev->dev.of_node) { + mmc->caps |= MMC_CAP_SDIO_IRQ; + if (of_find_property(host->dev->of_node, + "ti,quirk-swakeup-missing", NULL)) { + /* no wakeup from deeper power states, use polling */ + mmc->caps &= ~MMC_CAP_SDIO_IRQ; + } + } + omap_hsmmc_protect_card(host); mmc_add_host(mmc);