From patchwork Thu Dec 12 20:30:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 3334271 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AA34B9F2A9 for ; Thu, 12 Dec 2013 21:07:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1E979207E4 for ; Thu, 12 Dec 2013 21:07:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 603F6207D1 for ; Thu, 12 Dec 2013 21:07:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751919Ab3LLVG6 (ORCPT ); Thu, 12 Dec 2013 16:06:58 -0500 Received: from va3ehsobe010.messaging.microsoft.com ([216.32.180.30]:2293 "EHLO va3outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751840Ab3LLVG4 (ORCPT ); Thu, 12 Dec 2013 16:06:56 -0500 Received: from mail24-va3-R.bigfish.com (10.7.14.251) by VA3EHSOBE007.bigfish.com (10.7.40.11) with Microsoft SMTP Server id 14.1.225.22; Thu, 12 Dec 2013 21:06:45 +0000 Received: from mail24-va3 (localhost [127.0.0.1]) by mail24-va3-R.bigfish.com (Postfix) with ESMTP id 420DE2000DD; Thu, 12 Dec 2013 21:06:45 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.231; KIP:(null); UIP:(null); IPV:NLI; H:sj-itexedge01.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 11 X-BigFish: VS11(zzzz1f42h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hz70kz1de098h8275bh1de097hz2fh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah224fh1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h286p1155h) Received-SPF: pass (mail24-va3: domain of altera.com designates 66.35.236.231 as permitted sender) client-ip=66.35.236.231; envelope-from=dinguyen@altera.com; helo=sj-itexedge01.altera.priv.altera.com ; v.altera.com ; Received: from mail24-va3 (localhost.localdomain [127.0.0.1]) by mail24-va3 (MessageSwitch) id 1386882403850974_10850; Thu, 12 Dec 2013 21:06:43 +0000 (UTC) Received: from VA3EHSMHS026.bigfish.com (unknown [10.7.14.249]) by mail24-va3.bigfish.com (Postfix) with ESMTP id A9E6F2A008B; Thu, 12 Dec 2013 21:06:43 +0000 (UTC) Received: from sj-itexedge01.altera.priv.altera.com (66.35.236.231) by VA3EHSMHS026.bigfish.com (10.7.99.36) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 12 Dec 2013 21:06:43 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by sj-itexedge01.altera.priv.altera.com (66.35.236.231) with Microsoft SMTP Server id 8.3.298.1; Thu, 12 Dec 2013 12:58:14 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id e063HToO010208; Wed, 5 Jan 2000 19:17:34 -0800 (PST) From: To: , , , , , , , , , , , , , CC: , , , , Dinh Nguyen Subject: [PATCHv6 1/5] mmc: dw_mmc: Add support to set the SDR and DDR timing through clock framework Date: Thu, 12 Dec 2013 14:30:41 -0600 Message-ID: <1386880245-10192-2-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1386880245-10192-1-git-send-email-dinguyen@altera.com> References: <1386880245-10192-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen All implementations of the Synopsys DW SD/MMC IP have settings to control the phase shift of the CIU clk. These phase shift settings are necessary for the SD/MMC to correctly clock the card. All variants of the dw_mmc will need these settings, but how they are implemented can vastly vary. This patch enables the setting for the SDR and/or DDR settings through the common clock framework. Depends on the patch "mmc: dw_mmc: Enable the hold reg for certain speed modes", that is already reading the "samsung,dw-mshc-sdr-timing" and "samsung,dw-mshc-ddr-timing" bindings, this patch saves those values into a u32 bitmask that can be passed to the clock framework to use. Signed-off-by: Dinh Nguyen --- v6: Add this patch v5: none v4: none v3: none v2: none --- drivers/mmc/host/dw_mmc.c | 23 +++++++++++++++++++++++ include/linux/mmc/dw_mmc.h | 6 ++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 480dafe..1fb5cff 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2431,6 +2431,8 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) if ((sdr_timing[1] == 0) || (ddr_timing[1] == 0)) pdata->cclk_in_drv = 0; + pdata->sdr_timing = (sdr_timing[1] | (sdr_timing[0] << 4)); + pdata->ddr_timing = (ddr_timing[1] | (ddr_timing[0] << 4)); return pdata; } @@ -2478,6 +2480,27 @@ int dw_mci_probe(struct dw_mci *host) dev_dbg(host->dev, "ciu clock not available\n"); host->bus_hz = host->pdata->bus_hz; } else { + /* If the CIU clk is available, we check for SDR and DDR + * timing phase shift settings. But not all platforms + * may have populated these settings, the driver will not fail + * if these settings are not specified. + */ + if (host->pdata->sdr_timing) { + host->sdr_clk = devm_clk_get(host->dev, "sdr_mmc_clk"); + if (IS_ERR(host->sdr_clk)) + dev_dbg(host->dev, "sdr_mmc clock not available\n"); + else + clk_set_rate(host->sdr_clk, host->pdata->sdr_timing); + } + + if (host->pdata->ddr_timing) { + host->ddr_clk = devm_clk_get(host->dev, "ddr_mmc_clk"); + if (IS_ERR(host->ddr_clk)) + dev_dbg(host->dev, "ddr_mmc clock not available\n"); + else + clk_set_rate(host->ddr_clk, host->pdata->ddr_timing); + } + ret = clk_prepare_enable(host->ciu_clk); if (ret) { dev_err(host->dev, "failed to enable ciu clock\n"); diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h index 2b5b8bf..ad90ad1 100644 --- a/include/linux/mmc/dw_mmc.h +++ b/include/linux/mmc/dw_mmc.h @@ -83,6 +83,8 @@ struct mmc_data; * @priv: Implementation defined private data. * @biu_clk: Pointer to bus interface unit clock instance. * @ciu_clk: Pointer to card interface unit clock instance. + * @sdr_clk: Pointer to the SDR clock instance. + * @ddr_clk: Pointer to the DDR clock instance. * @slot: Slots sharing this MMC controller. * @fifo_depth: depth of FIFO. * @data_shift: log2 of FIFO item size. @@ -170,6 +172,8 @@ struct dw_mci { void *priv; struct clk *biu_clk; struct clk *ciu_clk; + struct clk *sdr_clk; + struct clk *ddr_clk; struct dw_mci_slot *slot[MAX_MCI_SLOTS]; /* FIFO push and pull */ @@ -241,6 +245,8 @@ struct dw_mci_board { u32 caps2; /* More capabilities */ u32 pm_caps; /* PM capabilities */ u32 cclk_in_drv; /*cclk_in_drv phase shift */ + u32 sdr_timing; /* Single data rate timing setting. */ + u32 ddr_timing; /* Double data rate timing setting. */ /* * Override fifo depth. If 0, autodetect it from the FIFOTH register, * but note that this may not be reliable after a bootloader has used