From patchwork Fri Feb 28 11:24:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 3740191 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C066CBF13A for ; Fri, 28 Feb 2014 11:26:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EA4B12026F for ; Fri, 28 Feb 2014 11:26:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 139B820237 for ; Fri, 28 Feb 2014 11:26:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751449AbaB1LZQ (ORCPT ); Fri, 28 Feb 2014 06:25:16 -0500 Received: from ns.mm-sol.com ([37.157.136.199]:49009 "EHLO extserv.mm-sol.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751522AbaB1LZO (ORCPT ); Fri, 28 Feb 2014 06:25:14 -0500 Received: from mms.wifi.mm-sol.com (unknown [37.157.136.206]) by extserv.mm-sol.com (Postfix) with ESMTPSA id 2D4524F881; Fri, 28 Feb 2014 13:25:13 +0200 (EET) From: Georgi Djakov To: linux-mmc@vger.kernel.org, cjb@laptop.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, grant.likely@linaro.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, swarren@wwwdotorg.org, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, rob@landley.net Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Georgi Djakov Subject: [PATCH v9 1/3] mmc: sdhci-msm: Qualcomm SDHCI binding documentation Date: Fri, 28 Feb 2014 13:24:33 +0200 Message-Id: <1393586675-14628-2-git-send-email-gdjakov@mm-sol.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1393586675-14628-1-git-send-email-gdjakov@mm-sol.com> References: <1393586675-14628-1-git-send-email-gdjakov@mm-sol.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-3.8 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the device-tree binding documentation for Qualcomm SDHCI driver. It contains the differences between the core properties in mmc.txt and the properties used by the sdhci-msm driver. Signed-off-by: Georgi Djakov --- .../devicetree/bindings/mmc/sdhci-msm.txt | 80 ++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-msm.txt diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt new file mode 100644 index 0000000..d136cb7 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -0,0 +1,80 @@ +* Qualcomm SDHCI controller (sdhci-msm) + +This file documents differences between the core properties in mmc.txt +and the properties used by the sdhci-msm driver. + +Required properties: +- compatible: Should contain "qcom,sdhci-msm-v4". +- reg: Base address and length of the register set listed in reg-names. +- reg-names: Should contain the following: + "hc_mem" - Host controller register map + "core_mem" - SD Core register map +- interrupts: Should contain an interrupt-specifiers for the interrupts listed in interrupt-names. +- interrupt-names: Should contain the following: + "hc_irq" - Host controller interrupt + "pwr_irq" - PMIC interrupt +- vdd-supply: Phandle to the regulator for the vdd (core voltage) supply. +- vdd-io-supply: Phandle to the regulator for the vdd-io (i/o voltage) supply. +- pinctrl-names: Should contain only one value - "default". +- pinctrl-0: Should specify pin control groups used for this controller. +- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names. +- clock-names: Should contain the following: + "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required) + "core" - SDC MMC clock (MCLK) (required) + "bus" - SDCC bus voter clock (optional) + +Optional properties: + +- qcom,vdd-voltage-min - Specifies the minimum core voltage supported by the device in microvolts. +- qcom,vdd-voltage-max - Specifies the maximum core voltage supported by the device in microvolts. +- qcom,vdd-io-voltage-min - Specifies the minimum i/o voltage supported by the device in microvolts. +- qcom,vdd-io-voltage-max - Specifies the maximum i/o voltage supported by the device in microvolts. + +Example: + + sdhc_1: sdhci@f9824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + bus-width = <8>; + non-removable; + + vdd-supply = <&pm8941_l20>; + vdd-io-supply = <&pm8941_s3>; + + qcom,vdd-voltage-min = <2950000>; + qcom,vdd-voltage-max = <2950000>; + qcom,vdd-io-voltage-min = <1800000>; + qcom,vdd-io-voltage-max = <1800000>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + }; + + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + bus-width = <4>; + + vdd-supply = <&pm8941_l21>; + vdd-io-supply = <&pm8941_l13>; + + qcom,vdd-voltage-min = <2950000>; + qcom,vdd-voltage-max = <2950000>; + qcom,vdd-io-voltage-min = <1800000>; + qcom,vdd-io-voltage-max = <2950000>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + };