From patchwork Wed Mar 26 11:46:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuvaraj CD X-Patchwork-Id: 3892961 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D3188BF540 for ; Wed, 26 Mar 2014 11:46:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0B2862017B for ; Wed, 26 Mar 2014 11:46:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 67F6420221 for ; Wed, 26 Mar 2014 11:46:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754026AbaCZLq2 (ORCPT ); Wed, 26 Mar 2014 07:46:28 -0400 Received: from mail-pd0-f176.google.com ([209.85.192.176]:57651 "EHLO mail-pd0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753545AbaCZLq1 (ORCPT ); Wed, 26 Mar 2014 07:46:27 -0400 Received: by mail-pd0-f176.google.com with SMTP id r10so1762603pdi.35 for ; Wed, 26 Mar 2014 04:46:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=Ck3H6f0GPlbJr+MM7wxFWliCRlSkVSkczXGmeJxejlk=; b=Qx8rM2SzEH8LrFo6ki2v6J5DFjfPyDfn5gOFVZOaC70CW5FJMoi6VBphnfvAlYhyD+ sUpRvJcRVHBD7aVvHHfRmbbFFiQZCK4eacFVIqTWfp1DxehGwTMuS4nUwF7tlPgZq+5Q 0UkvkHA+LqSkheiuMQO8W8E1YJ55QOAMmdJAY/ScGJrqJFSZHsMYZNcWKtm/bXbM2WlP /5KWTIgYMjNsGk7UOcXEoaPciwBHC8OXSZsBx2cS0E0bZN8XAePV0ZDPJZnpIsHP7Pe4 je7zQfTH9HTv2NGw3nFAySuHmj+kbzPe2rjtGWnAP/3iAIsCgQbKjL4orQL4fgxCG7Di RwCQ== X-Received: by 10.68.202.194 with SMTP id kk2mr17731001pbc.156.1395834387180; Wed, 26 Mar 2014 04:46:27 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id ix2sm57203745pbc.45.2014.03.26.04.46.22 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 26 Mar 2014 04:46:26 -0700 (PDT) From: Yuvaraj Kumar C D To: grundler@chromium.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jh80.chung@samsung.com, cjb@laptop.org, tgih.jun@samsung.com, linux-mmc@vger.kernel.org, sonnyrao@chromium.org, kgene.kim@samsung.com, joshi@samsung.com Cc: t.figa@samsung.com, Yuvaraj Kumar C D Subject: [PATCH] mmc: dw_mmc: change to use recommended reset procedure Date: Wed, 26 Mar 2014 17:16:14 +0530 Message-Id: <1395834374-1988-1-git-send-email-yuvaraj.cd@samsung.com> X-Mailer: git-send-email 1.7.10.4 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sonny Rao This patch changes the fifo reset code to follow the reset procedure outlined in the documentation of Synopsys Mobile storage host databook 7.2.13. Without this patch, we could able to see eMMC was not detected after multiple reboots due to driver hangs while eMMC tuning for HS200. Signed-off-by: Sonny Rao Signed-off-by: Yuvaraj Kumar C D --- drivers/mmc/host/dw_mmc.c | 48 ++++++++++++++++++++++++++++++++++++++++++++- drivers/mmc/host/dw_mmc.h | 1 + 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 32dd81d..1d77431 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2220,7 +2220,53 @@ static inline bool dw_mci_fifo_reset(struct dw_mci *host) host->sg = NULL; } - return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET); + /* + * The recommended method for resetting is to always reset the + * controller and the fifo, but differs slightly depending on the mode. + * Note that this doesn't handle the "generic DMA" (not IDMAC) case. + */ + if (dw_mci_ctrl_reset(host, SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET)) { + unsigned long timeout = jiffies + msecs_to_jiffies(500); + u32 status, rint; + + /* if using dma we wait for dma_req to clear */ + if (host->using_dma) { + do { + status = mci_readl(host, STATUS); + if (!(status & SDMMC_STATUS_DMA_REQ)) + break; + cpu_relax(); + } while (time_before(jiffies, timeout)); + + if (status & SDMMC_STATUS_DMA_REQ) + dev_err(host->dev, + "%s: Timeout waiting for dma_req to " + "clear during reset", __func__); + + /* when using DMA next we reset the fifo again */ + dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET); + } + /* + * In all cases we clear the RAWINTS register to clear any + * interrupts. + */ + rint = mci_readl(host, RINTSTS); + rint = rint & (~mci_readl(host, MINTSTS)); + if (rint) + mci_writel(host, RINTSTS, rint); + + } else + dev_err(host->dev, "%s: Reset bits didn't clear", __func__); + + #ifdef CONFIG_MMC_DW_IDMAC + /* It is also recommended that we reset and reprogram idmac */ + dw_mci_idmac_reset(host); + #endif + + /* After a CTRL reset we need to have CIU set clock registers */ + mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); + + return true; } static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host) diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 738fa24..037e47a 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -129,6 +129,7 @@ #define SDMMC_CMD_INDX(n) ((n) & 0x1F) /* Status register defines */ #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) +#define SDMMC_STATUS_DMA_REQ BIT(31) /* FIFOTH register defines */ #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ ((r) & 0xFFF) << 16 | \