From patchwork Tue Apr 15 01:42:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 3988231 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0DEFB9F2CC for ; Tue, 15 Apr 2014 01:44:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4F1162020A for ; Tue, 15 Apr 2014 01:43:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7A467201F9 for ; Tue, 15 Apr 2014 01:43:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753718AbaDOBm5 (ORCPT ); Mon, 14 Apr 2014 21:42:57 -0400 Received: from mail-pb0-f74.google.com ([209.85.160.74]:62774 "EHLO mail-pb0-f74.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753566AbaDOBmx (ORCPT ); Mon, 14 Apr 2014 21:42:53 -0400 Received: by mail-pb0-f74.google.com with SMTP id md12so1145717pbc.3 for ; Mon, 14 Apr 2014 18:42:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7rUXcrCZpWiMrjW5mECbHYWcCC6Cct9yxf3PByl9Lw8=; b=XQk4q/7vLqE149F6A5QfMBMdruIL3+pqhrw1WDeoVzhAAUFe9Yka66XgS9ar59nm/x lEgBTXlYXcq4mG7qqoG8rFGPYmbJIa+bW6Bc3yyr6Sz+vNoGMbfRUhXDQirAi9Iw7yt5 XYGrk1miwnLnqwHvT2nx4RLlKaxN++sdYxcJ1dzAJm62jbmTZPwR/LlOVstCobWmkYr8 Dgv6ZO7nnvluymCdeFKA78VPmxB9x/AksZq09VV1mAJwfP8HLmN4t9NiBp69KPppv187 j3aqJTsBOJzQGO5ydUMTi+5wgBME1V2xkEQJRTy07J2g7sDopnGO7dNiER1dlZ67n8dl iW8A== X-Gm-Message-State: ALoCoQnMCWDQY0qf6GMlmn/mgKD3Aegu+BDTXzoj9MVTJfT8zPHQm889YNx9j6K+Zhwkcb90ICYctUlFCKXPHgZV/tgYesKNjU6tve5icJdfTWJdsdmhlMVOdRByCD0YLHxjo5po5p8NwjtHTlEbxDsvG8IPrYpamjBCt02i5PvhDdfjlR07rop2Dz1sFdDEH3wfYxBY2Wci81DI4s7Z1X4b4aDSyCVVTQ== X-Received: by 10.66.232.38 with SMTP id tl6mr12766978pac.33.1397526173284; Mon, 14 Apr 2014 18:42:53 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id e40si2521631yhf.0.2014.04.14.18.42.53 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Apr 2014 18:42:53 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 12A9F31C1E3; Mon, 14 Apr 2014 18:42:53 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id CA9DA220757; Mon, 14 Apr 2014 18:42:52 -0700 (PDT) From: Andrew Bresticker To: Stephen Warren , Thierry Reding , Chris Ball , Ulf Hansson Cc: linux-mmc@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Bresticker Subject: [PATCH 2/4] mmc: tegra: fix reporting of base clock frequency Date: Mon, 14 Apr 2014 18:42:41 -0700 Message-Id: <1397526163-20126-3-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.9.1.423.g4596e3a In-Reply-To: <1397526163-20126-1-git-send-email-abrestic@chromium.org> References: <1397526163-20126-1-git-send-email-abrestic@chromium.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra SDHCI controllers, by default, report a base clock frequency of 208Mhz in SDHCI_CAPABILTIES which may or may not be equal to the actual base clock frequency. While this can be overridden by setting BASE_CLK_FREQ in VENDOR_CLOCK_CTRL on Tegra30 and later SoCs, just set SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN and supply a get_max_clock() callback to get the actual rate of the base clock. Signed-off-by: Andrew Bresticker --- drivers/mmc/host/sdhci-tegra.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 3cadd9c..c3f92d9 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -165,13 +165,15 @@ static const struct sdhci_ops tegra_sdhci_ops = { .write_l = tegra_sdhci_writel, .platform_bus_width = tegra_sdhci_buswidth, .platform_reset_exit = tegra_sdhci_reset_exit, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, }; static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_NO_HISPD_BIT | - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, .ops = &tegra_sdhci_ops, }; @@ -186,7 +188,8 @@ static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_NO_HISPD_BIT | - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, .ops = &tegra_sdhci_ops, }; @@ -202,7 +205,8 @@ static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_NO_HISPD_BIT | - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, .ops = &tegra_sdhci_ops, };