From patchwork Mon Apr 21 21:49:05 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 4026581 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A5B36BFF02 for ; Mon, 21 Apr 2014 21:49:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D8FE520357 for ; Mon, 21 Apr 2014 21:49:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0B161201EF for ; Mon, 21 Apr 2014 21:49:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754952AbaDUVtS (ORCPT ); Mon, 21 Apr 2014 17:49:18 -0400 Received: from mail-we0-f182.google.com ([74.125.82.182]:41771 "EHLO mail-we0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754949AbaDUVtM (ORCPT ); Mon, 21 Apr 2014 17:49:12 -0400 Received: by mail-we0-f182.google.com with SMTP id q59so1068539wes.27 for ; Mon, 21 Apr 2014 14:49:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y95zCNwaYwcHkU4eH1jgI/Y+Cc8k+JV42ANN1ierZgE=; b=JHmAC2XARTV1re2CDI3hlSl7Q7KDCL3iwSgaCQw9BlQpS7Bw2jIoKyB7vV6ZhkeH91 Gv2jAPODa8mhGwpeV5i4godUWWSIbcXnQP2DTZBGEAGR+rCkW6pS/3lIt449S3DZ4/Aw 9uiBkoMMCtsMCJYhd2vOZWXjziydlm7azmSjbLfmlQoyOCVJkPb39t+pMjCPIlChR9jm iTNKvczOgbI+Raqk/Y2SATpecMJyV5OYi/PHHZPana565P8d+cTjyFRKfSAREB4qDIJ5 Tdn86sCZDU3hoUEgYtaOze6uKU65pQE/nMpq2Jlun1ZQ+fDOZ7ttEjzzsWTfwZKAGM+/ TeiQ== X-Gm-Message-State: ALoCoQmR16fkWo1R4n/ynMGzmxm0JjtpIPDBpk9vc/N5pMjHCXqbJ4J1JSkgVU74RyB4NNhDvFHW X-Received: by 10.194.161.168 with SMTP id xt8mr30430907wjb.35.1398116951450; Mon, 21 Apr 2014 14:49:11 -0700 (PDT) Received: from srinivas-Inspiron-N5050.dlink.com (host-78-149-8-254.as13285.net. [78.149.8.254]) by mx.google.com with ESMTPSA id hm5sm58833850wjc.17.2014.04.21.14.49.10 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 21 Apr 2014 14:49:10 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: linux-mmc@vger.kernel.org Cc: Russell King , Chris Ball , Ulf Hansson , linux-kernel@vger.kernel.org, agross@quicinc.com, linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH RFC 10/12] mmc: mmci: Add clock support for Qualcomm. Date: Mon, 21 Apr 2014 22:49:05 +0100 Message-Id: <1398116945-31640-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398116624-31052-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1398116624-31052-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla MCICLK going to card bus is directly driven by the clock controller, so the driver has to set the required rates depending on the state of the card. This bit of support is very much similar to bypass mode but there is no such thing called bypass mode in MCICLK register of Qcom SD card controller. By default the clock is directly driven by the clk controller. This patch adds clock support for Qualcomm SDCC in the driver. This bit of code is conditioned on hw designer. Signed-off-by: Srinivas Kandagatla --- drivers/mmc/host/mmci.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index f465eb5..2cd3a8f 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -291,7 +291,18 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) host->cclk = 0; if (desired) { - if (desired >= host->mclk) { + if (desired != host->mclk && + host->hw_designer == AMBA_VENDOR_QCOM) { + /* Qcom MCLKCLK register does not define bypass bits */ + int rc = clk_set_rate(host->clk, desired); + if (rc < 0) { + dev_err(mmc_dev(host->mmc), + "Error setting clock rate (%d)\n", rc); + } else { + host->mclk = clk_get_rate(host->clk); + host->cclk = host->mclk; + } + } else if (desired >= host->mclk) { clk = MCI_CLK_BYPASS; if (variant->st_clkdiv) clk |= MCI_ST_UX500_NEG_EDGE; @@ -1612,7 +1623,8 @@ static int mmci_probe(struct amba_device *dev, * of course. */ if (plat->f_max) - mmc->f_max = min(host->mclk, plat->f_max); + mmc->f_max = (host->hw_designer == AMBA_VENDOR_QCOM) ? + plat->f_max : min(host->mclk, plat->f_max); else mmc->f_max = min(host->mclk, fmax); dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);