From patchwork Thu May 15 09:37:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 4180491 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 01920C0ACC for ; Thu, 15 May 2014 09:40:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 30B8C20306 for ; Thu, 15 May 2014 09:40:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 274032037E for ; Thu, 15 May 2014 09:40:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754420AbaEOJhc (ORCPT ); Thu, 15 May 2014 05:37:32 -0400 Received: from mail-wi0-f174.google.com ([209.85.212.174]:46324 "EHLO mail-wi0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754563AbaEOJh2 (ORCPT ); Thu, 15 May 2014 05:37:28 -0400 Received: by mail-wi0-f174.google.com with SMTP id r20so9453346wiv.13 for ; Thu, 15 May 2014 02:37:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IJuMMPryl+cRR4nHAV8f7T2xhIoC97VnZStiH5cXTHQ=; b=FEfBP2PDXwB3OyujhFzJmf78c7bkhYm92oN4cLti6H0YXSshT/oF40+f3zaPsY/HDo toTRNDqLO2LjdPdbPPLRZjDS/7j9h7aJXNxz2IQBKV3hwUYUo9nomjpHjgjtwONK7qwv 5or/vwHUELF666PBl3cM0N3/oIQnV3ICd7/nZdRdM7qBsjA0Q2zcvaEIRAT4lru44eEq UMeaRbZq9Ab5xe740hg+ZIUkPM9UCTw/bVdOAn5kxvLK1ChPJT0Ho3rsLIhcqY2eBd7f 6F/hVrSEQtXQ3kQIe7YWOsqc1Hv/fz7YANJOcv6yAfExaO2RNU+vpttOI6pEJwmpMthq vYvw== X-Gm-Message-State: ALoCoQnFWxWW4uE0QFpkvf3aVGMBypDzb+nsc7URCpRJj7rq7Fgv4Ka4Ad30lL1S6+zONZVor0fb X-Received: by 10.194.88.106 with SMTP id bf10mr7714509wjb.26.1400146646776; Thu, 15 May 2014 02:37:26 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-78-145-240-98.as13285.net. [78.145.240.98]) by mx.google.com with ESMTPSA id em5sm8839141wic.23.2014.05.15.02.37.25 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 May 2014 02:37:26 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Russell King , Ulf Hansson , linux-mmc@vger.kernel.org Cc: Chris Ball , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linus.walleij@linaro.org, Srinivas Kandagatla Subject: [PATCH v2 09/14] mmc: mmci: add edge support to data and command out in variant data. Date: Thu, 15 May 2014 10:37:23 +0100 Message-Id: <1400146643-30179-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1400146447-29803-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1400146447-29803-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla This patch adds edge support for data and command out to variant structure giving more flexibility to the driver to support more SOCs which have different clock register layout. Without this patch other new SOCs like Qcom will have to add more code to special case them Signed-off-by: Srinivas Kandagatla Reviewed-by: Linus Walleij --- drivers/mmc/host/mmci.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index a81f303..17e7f6a 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -53,6 +53,7 @@ static unsigned int fmax = 515633; * @clkreg: default value for MCICLOCK register * @clkreg_enable: enable value for MMCICLOCK register * @clkreg_8bit_bus_enable: enable value for 8 bit bus + * @clkreg_neg_edge_enable: enable value for inverted data/cmd output * @datalength_bits: number of bits in the MMCIDATALENGTH register * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY * is asserted (likewise for RX) @@ -76,6 +77,7 @@ struct variant_data { unsigned int clkreg; unsigned int clkreg_enable; unsigned int clkreg_8bit_bus_enable; + unsigned int clkreg_neg_edge_enable; unsigned int datalength_bits; unsigned int fifosize; unsigned int fifohalfsize; @@ -148,6 +150,7 @@ static struct variant_data variant_ux500 = { .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, + .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 24, .sdio = true, @@ -165,6 +168,7 @@ static struct variant_data variant_ux500v2 = { .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, + .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 24, .sdio = true, @@ -348,7 +352,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) clk |= variant->clkreg_8bit_bus_enable; if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) - clk |= MCI_ST_UX500_NEG_EDGE; + clk |= variant->clkreg_neg_edge_enable; mmci_write_clkreg(host, clk); }