From patchwork Thu May 22 15:18:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 4223731 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E2B2D9F23C for ; Thu, 22 May 2014 15:19:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 013782037A for ; Thu, 22 May 2014 15:19:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0523220379 for ; Thu, 22 May 2014 15:19:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752314AbaEVPS4 (ORCPT ); Thu, 22 May 2014 11:18:56 -0400 Received: from mail-wi0-f177.google.com ([209.85.212.177]:56413 "EHLO mail-wi0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752159AbaEVPSx (ORCPT ); Thu, 22 May 2014 11:18:53 -0400 Received: by mail-wi0-f177.google.com with SMTP id f8so4492207wiw.10 for ; Thu, 22 May 2014 08:18:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AQ0woji+F6RC8LDBPrCs0OX+HnJKkoSTUiW2iX0Kce0=; b=GUXqhCn/JfsPah95+9TrjKUtrPL6h8BBu/yBRshbxg8VLAyD3do+UO3i9LiU2ILPD+ nxCMmxzBiJVMaJ2kB9YEQPRTOPJFiKwYnZgxY2WVUXGP+gje2t/PdpaBE1z8v4NIdUHb Ib1WavA5HJ7PlKIrzmerEAn8Ir5bP/uAWPk3s8IZl0xQz00s4CWOX9jm/R/FPO7PltaN GnzYR1785WVCYN2VMlHLvqZl0UqclgNn38b/0L2OrlIBn39yBIHUrMPEJ2hH3usBz4Z8 8eBDdNkmh+0QTVjuk+y2x0MIWi3FpZS68nGi4C6PYUlKKUwzzoMlTffAm+dQYXaiJVSK lZBA== X-Gm-Message-State: ALoCoQn0E37pi+5mtn2tjNPfb8DLdH/c2ZOrjiup9nveQs3+SML/OBdKgQUSFDRo7OA2C2kO02Wp X-Received: by 10.180.106.194 with SMTP id gw2mr17100349wib.47.1400771931913; Thu, 22 May 2014 08:18:51 -0700 (PDT) Received: from localhost.localdomain (cpc14-aztw22-2-0-cust189.18-1.cable.virginm.net. [82.45.1.190]) by mx.google.com with ESMTPSA id dk4sm848205wib.14.2014.05.22.08.18.50 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 May 2014 08:18:51 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.coquelin@st.com, patrice.chotard@st.com, srinivas.kandagatla@gmail.com, chris@printf.net, ulf.hansson@linaro.org Cc: peter.griffin@linaro.org, kernel@stlinux.com, lee.jones@linaro.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Giuseppe Cavallaro Subject: [PATCH 5/8] ARM: STi: DT: Add sdhci pin configuration for stih415 Date: Thu, 22 May 2014 16:18:19 +0100 Message-Id: <1400771902-26553-6-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1400771902-26553-1-git-send-email-peter.griffin@linaro.org> References: <1400771902-26553-1-git-send-email-peter.griffin@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the required pin config for the sdhci controller present in the stih415 SoC. Signed-off-by: Peter Griffin Signed-off-by: Giuseppe Cavallaro --- arch/arm/boot/dts/stih415-pinctrl.dtsi | 21 +++++++++++++++++++++ arch/arm/boot/dts/stih415.dtsi | 12 ++++++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index caeac7e..eee2373 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -429,6 +429,27 @@ }; }; }; + + mmc0 { + pinctrl_mmc0: mmc0 { + st,pins { + mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&PIO14 4 ALT4 BIDIR_PU BYPASS 0>; + data1 = <&PIO14 5 ALT4 BIDIR_PU BYPASS 0>; + data2 = <&PIO14 6 ALT4 BIDIR_PU BYPASS 0>; + data3 = <&PIO14 7 ALT4 BIDIR_PU BYPASS 0>; + cmd = <&PIO15 1 ALT4 BIDIR_PU BYPASS 0>; + wp = <&PIO15 3 ALT4 IN>; + data4 = <&PIO16 4 ALT4 BIDIR_PU BYPASS 0>; + data5 = <&PIO16 5 ALT4 BIDIR_PU BYPASS 0>; + data6 = <&PIO16 6 ALT4 BIDIR_PU BYPASS 0>; + data7 = <&PIO16 7 ALT4 BIDIR_PU BYPASS 0>; + pwr = <&PIO17 1 ALT4 OUT>; + cd = <&PIO17 2 ALT4 IN>; + led = <&PIO17 3 ALT4 OUT>; + }; + }; + }; }; pin-controller-left { diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index d6f254f..6579b1d 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi @@ -218,5 +218,17 @@ resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, <&softreset STIH415_KEYSCAN_SOFTRESET>; }; + + mmc0: sdhci@fe81e000 { + compatible = "st,sdhci"; + status = "disabled"; + reg = <0xfe81e000 0x1000>; + interrupts = ; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0>; + clock-names = "mmc"; + clocks = <&clk_s_a1_ls 1>; + }; }; };