From patchwork Fri May 23 12:52:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 4232311 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C370C9F32B for ; Fri, 23 May 2014 12:52:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CB8C220108 for ; Fri, 23 May 2014 12:52:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0B79E202C8 for ; Fri, 23 May 2014 12:52:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752795AbaEWMwP (ORCPT ); Fri, 23 May 2014 08:52:15 -0400 Received: from mail-wi0-f177.google.com ([209.85.212.177]:46090 "EHLO mail-wi0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752010AbaEWMwM (ORCPT ); Fri, 23 May 2014 08:52:12 -0400 Received: by mail-wi0-f177.google.com with SMTP id f8so808638wiw.4 for ; Fri, 23 May 2014 05:52:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=45PUDv7uBd955nkjJ5TQiDYBvOz1A7daxX4SL0zhI20=; b=GV4NM41u4xxIgr7tpunwx6AO69GQqSBpnFhF3QQdFVlXbwOHWKnZzkQ4GS9A3l9zHK 2+gNSxH5E8JyZimv2N/jzTFgqkt/j7UcysHlEh0iMl0Ol1zlNxh/iIjYfEZ2B48n+D9c cWhZu7mbhaaGL4kPFTq+GyrfWvyvRGzMz9osf7wGmvSOorbwgVH4lXSOdxHlazH4Y1Kd zzZtLVxP8WqTW+JaqhONTtUEr0OO5uue3Vc2IvBhHk1k8gzwttd6UXpVXL5Lq4OsTUab X/Og6Wgzu3DU3ezhm46BrsXptH78IJ95WCdZtwfkUaZTNRB///avBe142L/QEIopEmja l0NQ== X-Gm-Message-State: ALoCoQlrRm/XtRvqzMzoAzvW7+LOOrePY/V2vlQRYT+mhmg4nNDHXm5/RUn33m6EPhDnbc4k0PKr X-Received: by 10.180.19.201 with SMTP id h9mr3110666wie.17.1400849531249; Fri, 23 May 2014 05:52:11 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-78-149-4-211.as13285.net. [78.149.4.211]) by mx.google.com with ESMTPSA id dk4sm2805534wib.14.2014.05.23.05.52.09 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 23 May 2014 05:52:10 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Russell King , Ulf Hansson , linux-mmc@vger.kernel.org Cc: Chris Ball , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linus.walleij@linaro.org, Srinivas Kandagatla Subject: [PATCH v3 08/13] mmc: mmci: add 8bit bus support in variant data Date: Fri, 23 May 2014 13:52:07 +0100 Message-Id: <1400849527-7384-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1400849362-7007-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1400849362-7007-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla This patch adds 8bit bus enable to variant structure giving more flexibility to the driver to support more SOCs which have different clock register layout. Without this patch other new SOCs like Qcom will have to add more code to special case them. Signed-off-by: Srinivas Kandagatla Reviewed-by: Linus Walleij --- drivers/mmc/host/mmci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index dec70d2..a81f303 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -52,6 +52,7 @@ static unsigned int fmax = 515633; * struct variant_data - MMCI variant-specific quirks * @clkreg: default value for MCICLOCK register * @clkreg_enable: enable value for MMCICLOCK register + * @clkreg_8bit_bus_enable: enable value for 8 bit bus * @datalength_bits: number of bits in the MMCIDATALENGTH register * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY * is asserted (likewise for RX) @@ -74,6 +75,7 @@ static unsigned int fmax = 515633; struct variant_data { unsigned int clkreg; unsigned int clkreg_enable; + unsigned int clkreg_8bit_bus_enable; unsigned int datalength_bits; unsigned int fifosize; unsigned int fifohalfsize; @@ -116,6 +118,7 @@ static struct variant_data variant_u300 = { .fifosize = 16 * 4, .fifohalfsize = 8 * 4, .clkreg_enable = MCI_ST_U300_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 16, .sdio = true, @@ -144,6 +147,7 @@ static struct variant_data variant_ux500 = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 24, .sdio = true, @@ -160,6 +164,7 @@ static struct variant_data variant_ux500v2 = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 24, .sdio = true, @@ -340,7 +345,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) clk |= MCI_4BIT_BUS; if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) - clk |= MCI_ST_8BIT_BUS; + clk |= variant->clkreg_8bit_bus_enable; if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) clk |= MCI_ST_UX500_NEG_EDGE;