From patchwork Wed May 28 13:47:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 4255391 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6BF87BF90C for ; Wed, 28 May 2014 13:48:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 71C3B20138 for ; Wed, 28 May 2014 13:48:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B451420131 for ; Wed, 28 May 2014 13:48:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754414AbaE1NsG (ORCPT ); Wed, 28 May 2014 09:48:06 -0400 Received: from mail-wg0-f46.google.com ([74.125.82.46]:51680 "EHLO mail-wg0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754398AbaE1NsE (ORCPT ); Wed, 28 May 2014 09:48:04 -0400 Received: by mail-wg0-f46.google.com with SMTP id n12so11242340wgh.29 for ; Wed, 28 May 2014 06:48:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AdLatT/yyKMkSHvOrqTCy1baSmCv9fCLg74JdGVWQ7U=; b=Fx7LMXdQ3qLbyypwWWBP6vDX1WgHgypAQHHJL+0FYisAvPOOI7+uauQWiAG7MfC7dQ UR+cPz5AG7vtaZVShYdPQQbORCabxwTeUM0MhGsrDunUCuS7NSi84yLtI2uu88+VZiTM 6rwUrA3aCTOLZlpK5kavmEjI74EWzF724bG+nevLEN9owlkZx7TOjA3FqIOHQeCWy1mK GB661802l4EVLkvITCNStMXmSkiEDdr1sWDMRp4qWWIQU8I5QIpHFytxBs3JqEX1cF1S vI7E9LTPiS/kBWTl8fu8WxlWmb8goXs7Ww66t2xKVepTSSKs6UtO6sND6SjBdyy6G4oF pFNg== X-Gm-Message-State: ALoCoQnO6Ug4sBZJki99+CyeBHiwJCy7hysP1WqMuzBIx1K+8cSNtyBHL29ghLZfSRds+kCYad+e X-Received: by 10.194.89.40 with SMTP id bl8mr35490062wjb.90.1401284882804; Wed, 28 May 2014 06:48:02 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-78-149-4-211.as13285.net. [78.149.4.211]) by mx.google.com with ESMTPSA id fq2sm17064839wib.2.2014.05.28.06.48.00 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 May 2014 06:48:01 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Russell King , Ulf Hansson , linux-mmc@vger.kernel.org Cc: Chris Ball , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linus.walleij@linaro.org, Srinivas Kandagatla Subject: [PATCH v4 12/13] mmc: mmci: add explicit clk control Date: Wed, 28 May 2014 14:47:58 +0100 Message-Id: <1401284878-16937-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1401284608-16428-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1401284608-16428-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla On Controllers like Qcom SD card controller where cclk is mclk and mclk should be directly controlled by the driver. This patch adds support to control mclk directly in the driver, and also adds explicit_mclk_control flag in variant structure giving more flexibility to the driver. Signed-off-by: Srinivas Kandagatla --- drivers/mmc/host/mmci.c | 96 ++++++++++++++++++++++++++++++++----------------- drivers/mmc/host/mmci.h | 2 ++ 2 files changed, 65 insertions(+), 33 deletions(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 202f2d5..6eb0a29 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -72,6 +72,7 @@ static unsigned int fmax = 515633; * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock * @busy_detect: true if busy detection on dat0 is supported * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply + * @explicit_mclk_control: enable explicit mclk control in driver. */ struct variant_data { unsigned int clkreg; @@ -93,6 +94,7 @@ struct variant_data { bool pwrreg_clkgate; bool busy_detect; bool pwrreg_nopower; + bool explicit_mclk_control; }; static struct variant_data variant_arm = { @@ -199,6 +201,7 @@ static struct variant_data variant_qcom = { .datalength_bits = 24, .pwrreg_powerup = MCI_PWR_UP, .f_max = 208000000, + .explicit_mclk_control = true, }; static int mmci_card_busy(struct mmc_host *mmc) @@ -301,7 +304,9 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) host->cclk = 0; if (desired) { - if (desired >= host->mclk) { + if (variant->explicit_mclk_control) { + host->cclk = host->mclk; + } else if (desired >= host->mclk) { clk = MCI_CLK_BYPASS; if (variant->st_clkdiv) clk |= MCI_ST_UX500_NEG_EDGE; @@ -1340,6 +1345,18 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (!ios->clock && variant->pwrreg_clkgate) pwr &= ~MCI_PWR_ON; + if ((host->variant->explicit_mclk_control) && + (ios->clock != host->mclk_req)) { + int rc = clk_set_rate(host->clk, ios->clock); + if (rc < 0) { + dev_err(mmc_dev(host->mmc), + "Error setting clock rate (%d)\n", rc); + } else { + host->mclk = clk_get_rate(host->clk); + host->mclk_req = ios->clock; + } + } + spin_lock_irqsave(&host->lock, flags); mmci_set_clkreg(host, ios->clock); @@ -1490,19 +1507,6 @@ static int mmci_probe(struct amba_device *dev, host->plat = plat; host->variant = variant; host->mclk = clk_get_rate(host->clk); - /* - * According to the spec, mclk is max 100 MHz, - * so we try to adjust the clock down to this, - * (if possible). - */ - if (host->mclk > host->variant->f_max) { - ret = clk_set_rate(host->clk, host->variant->f_max); - if (ret < 0) - goto clk_disable; - host->mclk = clk_get_rate(host->clk); - dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", - host->mclk); - } host->phybase = dev->res.start; host->base = devm_ioremap_resource(&dev->dev, &dev->res); @@ -1511,25 +1515,51 @@ static int mmci_probe(struct amba_device *dev, goto clk_disable; } - /* - * The ARM and ST versions of the block have slightly different - * clock divider equations which means that the minimum divider - * differs too. - */ - if (variant->st_clkdiv) - mmc->f_min = DIV_ROUND_UP(host->mclk, 257); - else - mmc->f_min = DIV_ROUND_UP(host->mclk, 512); - /* - * If no maximum operating frequency is supplied, fall back to use - * the module parameter, which has a (low) default value in case it - * is not specified. Either value must not exceed the clock rate into - * the block, of course. - */ - if (mmc->f_max) - mmc->f_max = min(host->mclk, mmc->f_max); - else - mmc->f_max = min(host->mclk, fmax); + if (variant->explicit_mclk_control) { + /* get the nearest minimum clock to 100Khz */ + mmc->f_min = clk_round_rate(host->clk, 100000); + + if (mmc->f_max) + mmc->f_max = min(host->variant->f_max, mmc->f_max); + else + mmc->f_max = min(host->variant->f_max, fmax); + + } else { + /* + * According to the spec, mclk is max 100 MHz, + * so we try to adjust the clock down to this, + * (if possible). + */ + if (host->mclk > host->variant->f_max) { + ret = clk_set_rate(host->clk, host->variant->f_max); + if (ret < 0) + goto clk_disable; + host->mclk = clk_get_rate(host->clk); + dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", + host->mclk); + } + /* + * The ARM and ST versions of the block have slightly different + * clock divider equations which means that the minimum divider + * differs too. + */ + if (variant->st_clkdiv) + mmc->f_min = DIV_ROUND_UP(host->mclk, 257); + else + mmc->f_min = DIV_ROUND_UP(host->mclk, 512); + /* + * If no maximum operating frequency is supplied, fall back to + * use the module parameter, which has a (low) default value in + * case it is not specified. Either value must not exceed the + * clock rate into the block, of course. + */ + if (mmc->f_max) + mmc->f_max = min(host->mclk, mmc->f_max); + else + mmc->f_max = min(host->mclk, fmax); + + } + dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); /* Get regulators and the supported OCR mask */ diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index 706eb513..1882e20 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -208,6 +208,8 @@ struct mmci_host { spinlock_t lock; unsigned int mclk; + /* cached value of requested clk in set_ios */ + unsigned int mclk_req; unsigned int cclk; u32 pwr_reg; u32 pwr_reg_add;