From patchwork Fri Oct 3 15:55:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Hesselbarth X-Patchwork-Id: 5023511 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CD7EEC11AB for ; Fri, 3 Oct 2014 15:57:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 044D02017E for ; Fri, 3 Oct 2014 15:57:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 16405201BB for ; Fri, 3 Oct 2014 15:57:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754078AbaJCP4F (ORCPT ); Fri, 3 Oct 2014 11:56:05 -0400 Received: from mail-wi0-f171.google.com ([209.85.212.171]:47748 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754114AbaJCP4A (ORCPT ); Fri, 3 Oct 2014 11:56:00 -0400 Received: by mail-wi0-f171.google.com with SMTP id em10so5051739wid.10 for ; Fri, 03 Oct 2014 08:55:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EYHMW0nEld5//RvZE0Hm0LMNvqw8dDCBENOJ7hWg1vs=; b=L82NpqBJdWKgGRnw+3pUe0XiMBkmMqZgwejQrnJ0Lgwsf4hv4w5UP/OoCf5srPZ2fc W9bJ2R0a5djvhIcE/lk3sEPoBuwaWNtEy6N5IoW3Rq658H/oDmtZoUggZU0HTV1VIfid ccSpihLaKU+4+w9Qmg9jyQlJZn7XhVf3ITubc1TsO4Otudx3IL2DdkRtBwIVyLEacVk0 /YClNB5hmCpX2cSkKOj/3/pZ7zaUOLMTXKDB/M59OQ4Vedp4v6IRpPsX517mWe/mCx7X 8oIoD7rCqOa7MHLWbLh8tkBt7QTPwNjuE1yfTYxw+aNq0JJUjDhhd2HAP/Lsg+vhqSeU Bodg== X-Received: by 10.194.242.33 with SMTP id wn1mr8601600wjc.110.1412351758286; Fri, 03 Oct 2014 08:55:58 -0700 (PDT) Received: from topkick.lan (f051009242.adsl.alicedsl.de. [78.51.9.242]) by mx.google.com with ESMTPSA id x6sm2523610wif.0.2014.10.03.08.55.56 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Oct 2014 08:55:57 -0700 (PDT) From: Sebastian Hesselbarth To: Sebastian Hesselbarth Cc: Chris Ball , Ulf Hansson , Antoine Tenart , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/12] mmc: sdhci-pxav3: Document clocks and additional clock-names property Date: Fri, 3 Oct 2014 17:55:44 +0200 Message-Id: <1412351747-4188-10-git-send-email-sebastian.hesselbarth@gmail.com> In-Reply-To: <1412351747-4188-1-git-send-email-sebastian.hesselbarth@gmail.com> References: <1412351747-4188-1-git-send-email-sebastian.hesselbarth@gmail.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Now that sdhci-pxav3 driver allows to have more than one IP clock defined, document both clocks and clock-names properties. Signed-off-by: Sebastian Hesselbarth --- Cc: Chris Ball Cc: Ulf Hansson Cc: Antoine Tenart Cc: linux-mmc@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- Documentation/devicetree/bindings/mmc/sdhci-pxa.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt index 86223c3eda90..4dd6deb90719 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt @@ -12,6 +12,10 @@ Required properties: * for "marvell,armada-380-sdhci", two register areas. The first one for the SDHCI registers themselves, and the second one for the AXI/Mbus bridge registers of the SDHCI unit. +- clocks: Array of clocks required for SDHCI; requires at least one for + I/O clock. +- clock-names: Array of names corresponding to clocks property; shall be + "io" for I/O clock and "core" for optional core clock. Optional properties: - mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning. @@ -23,6 +27,8 @@ sdhci@d4280800 { reg = <0xd4280800 0x800>; bus-width = <8>; interrupts = <27>; + clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; + clock-names = "io", "core"; non-removable; mrvl,clk-delay-cycles = <31>; }; @@ -32,5 +38,6 @@ sdhci@d8000 { reg = <0xd8000 0x1000>, <0xdc000 0x100>; interrupts = <0 25 0x4>; clocks = <&gateclk 17>; + clock-names = "io"; mrvl,clk-delay-cycles = <0x1F>; };