From patchwork Fri Oct 3 15:55:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Hesselbarth X-Patchwork-Id: 5023561 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 16E4D9F38C for ; Fri, 3 Oct 2014 15:58:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 39E4E2017E for ; Fri, 3 Oct 2014 15:58:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5211B201C8 for ; Fri, 3 Oct 2014 15:58:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754121AbaJCPz7 (ORCPT ); Fri, 3 Oct 2014 11:55:59 -0400 Received: from mail-wg0-f44.google.com ([74.125.82.44]:56265 "EHLO mail-wg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754078AbaJCPz5 (ORCPT ); Fri, 3 Oct 2014 11:55:57 -0400 Received: by mail-wg0-f44.google.com with SMTP id y10so1841604wgg.3 for ; Fri, 03 Oct 2014 08:55:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IgoeXAnqIOtFxmg6d6+pQ+rc+bR6utzCyqknXrDyW8Y=; b=bnbdv47zBXonyG90+XyLPqemCXDf/nu8a0Uapq52i8fAF4j1Xem9q2q2AZogHdvcwi 70nOrff2TrAMGBq1thWTs6FwmBzFub2sV1PhPeqF5C6unCoTlXUPUmPx7jbYQIK/5sFx oeBvapiKhqDO670BkCoOWFPK9X4jCgWgf1Md8o4lVHQtbW1+CJ6GyBf4i1uwISL8JWSz 3WbobLb71WNdnoD/OzCrdjsrZMQgL85AZoZEABsaVNHgK94Wy8eGjVjy/XhC9FCfCySk mgKNJtxdw01kyeqRKnAw1iI9djR6+c9gr5JNZQAbjVnOXry5eJM09W54Iu97oX9WK1vF lUrQ== X-Received: by 10.180.8.229 with SMTP id u5mr13904455wia.76.1412351755562; Fri, 03 Oct 2014 08:55:55 -0700 (PDT) Received: from topkick.lan (f051009242.adsl.alicedsl.de. [78.51.9.242]) by mx.google.com with ESMTPSA id ji10sm2496972wid.7.2014.10.03.08.55.54 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Oct 2014 08:55:54 -0700 (PDT) From: Sebastian Hesselbarth To: Sebastian Hesselbarth Cc: Chris Ball , Ulf Hansson , Antoine Tenart , linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/12] mmc: sdhci-pxav3: Respect MMC_DDR52 timing on uhs signaling Date: Fri, 3 Oct 2014 17:55:37 +0200 Message-Id: <1412351747-4188-3-git-send-email-sebastian.hesselbarth@gmail.com> In-Reply-To: <1412351747-4188-1-git-send-email-sebastian.hesselbarth@gmail.com> References: <1412351747-4188-1-git-send-email-sebastian.hesselbarth@gmail.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP commit bb8175a8aa42d731a840cd474e348ac3367eb5a0 ("mmc: sdhci: clarify DDR timing mode between SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR mode to be distinguished from SD-UHS. While the differentation may be useful, pxav3 SDHCI controller lacks a corresponding check in its custom .set_uhs_signaling callback for MMC_DDR52. This patch adds a new switch case for MMC_TIMING_MMC_DDR52 to MMC_TIMING_UHS_DDR50 case. Signed-off-by: Sebastian Hesselbarth --- Cc: Chris Ball Cc: Ulf Hansson Cc: Antoine Tenart Cc: linux-mmc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/mmc/host/sdhci-pxav3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index 5036d7d39529..b55c807982fe 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -211,6 +211,7 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) case MMC_TIMING_UHS_SDR104: ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; break; + case MMC_TIMING_MMC_DDR52: case MMC_TIMING_UHS_DDR50: ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; break;