From patchwork Fri Oct 3 15:55:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Hesselbarth X-Patchwork-Id: 5023551 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 23DDB9F32B for ; Fri, 3 Oct 2014 15:58:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4A89A201BB for ; Fri, 3 Oct 2014 15:58:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5503D2017E for ; Fri, 3 Oct 2014 15:58:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754365AbaJCP53 (ORCPT ); Fri, 3 Oct 2014 11:57:29 -0400 Received: from mail-wi0-f173.google.com ([209.85.212.173]:38407 "EHLO mail-wi0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754109AbaJCPz7 (ORCPT ); Fri, 3 Oct 2014 11:55:59 -0400 Received: by mail-wi0-f173.google.com with SMTP id fb4so3240302wid.12 for ; Fri, 03 Oct 2014 08:55:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dSS7m+UGH0q4NzHIFeYn8z5VePPKph3RVEsHNw1vV84=; b=o/9r1C9W1p2OHzXIDnhX435L0KMn0JSCVX7i0fkCdDsYrnG3lRffmqJclDyto1B974 mHgi8FPVNeWykjD2Y57FZlZUWHl8lPVL+eEesFT+ky7uZ4NFT6y/tmnDBaHhOa3hy9wS c3epNbtAHW7rvPHXKkRghgJwwDfCWAms3cE0/hL0iUiHOmN41AART9C2f6IioN1zHMG5 MEBX1gzYct2FdnKQWcuhPZD4b3OiHLlXVxgn9vlRdZJwGEJlM6LIurb9VZpXgPG/ogFI p9gLc8dDBy4CdjPZUPZKNNfY8sC6P0uVWMY0YGZlh7jW4hxMvjJDwELh4TjaV17jEswg gUJg== X-Received: by 10.194.171.37 with SMTP id ar5mr8166750wjc.69.1412351757986; Fri, 03 Oct 2014 08:55:57 -0700 (PDT) Received: from topkick.lan (f051009242.adsl.alicedsl.de. [78.51.9.242]) by mx.google.com with ESMTPSA id fa7sm8374439wjd.27.2014.10.03.08.55.56 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Oct 2014 08:55:56 -0700 (PDT) From: Sebastian Hesselbarth To: Sebastian Hesselbarth Cc: Chris Ball , Ulf Hansson , Antoine Tenart , linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/12] mmc: sdhci-pxav3: Get optional core clock Date: Fri, 3 Oct 2014 17:55:43 +0200 Message-Id: <1412351747-4188-9-git-send-email-sebastian.hesselbarth@gmail.com> In-Reply-To: <1412351747-4188-1-git-send-email-sebastian.hesselbarth@gmail.com> References: <1412351747-4188-1-git-send-email-sebastian.hesselbarth@gmail.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Besides the I/O clock, some PXAv3 SDHCI IP also requires a core clock to be enabled. Add an optional core clock to the corresponding driver. Signed-off-by: Sebastian Hesselbarth --- Cc: Chris Ball Cc: Ulf Hansson Cc: Antoine Tenart Cc: linux-mmc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/mmc/host/sdhci-pxav3.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index 3dfd97977515..ad0badad0ebc 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -59,6 +59,7 @@ #define SDCE_MISC_INT_EN (1<<1) struct sdhci_pxa { + struct clk *clk_core; struct clk *clk_io; u8 power_mode; }; @@ -320,6 +321,10 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) pltfm_host->clk = pxa->clk_io; clk_prepare_enable(pxa->clk_io); + pxa->clk_core = devm_clk_get(dev, "core"); + if (!IS_ERR(pxa->clk_core)) + clk_prepare_enable(pxa->clk_core); + /* enable 1/8V DDR capable */ host->mmc->caps |= MMC_CAP_1_8V_DDR; @@ -392,6 +397,8 @@ err_add_host: err_of_parse: err_cd_req: clk_disable_unprepare(pxa->clk_io); + if (!IS_ERR(pxa->clk_core)) + clk_disable_unprepare(pxa->clk_core); err_clk_get: err_mbus_win: sdhci_pltfm_free(pdev); @@ -409,6 +416,8 @@ static int sdhci_pxav3_remove(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); clk_disable_unprepare(pxa->clk_io); + if (!IS_ERR(pxa->clk_core)) + clk_disable_unprepare(pxa->clk_core); sdhci_pltfm_free(pdev); @@ -456,6 +465,8 @@ static int sdhci_pxav3_runtime_suspend(struct device *dev) spin_unlock_irqrestore(&host->lock, flags); clk_disable_unprepare(pxa->clk_io); + if (!IS_ERR(pxa->clk_core)) + clk_disable_unprepare(pxa->clk_core); return 0; } @@ -468,6 +479,8 @@ static int sdhci_pxav3_runtime_resume(struct device *dev) unsigned long flags; clk_prepare_enable(pxa->clk_io); + if (!IS_ERR(pxa->clk_core)) + clk_prepare_enable(pxa->clk_core); spin_lock_irqsave(&host->lock, flags); host->runtime_suspended = false;