From patchwork Tue Oct 21 09:22:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sebastian Hesselbarth X-Patchwork-Id: 5112201 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DDED3C11AC for ; Tue, 21 Oct 2014 09:27:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1934C20103 for ; Tue, 21 Oct 2014 09:27:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 32B7E200F4 for ; Tue, 21 Oct 2014 09:27:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932273AbaJUJ0x (ORCPT ); Tue, 21 Oct 2014 05:26:53 -0400 Received: from mail-wi0-f182.google.com ([209.85.212.182]:50924 "EHLO mail-wi0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751479AbaJUJWx (ORCPT ); Tue, 21 Oct 2014 05:22:53 -0400 Received: by mail-wi0-f182.google.com with SMTP id bs8so423458wib.9 for ; Tue, 21 Oct 2014 02:22:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; bh=+moCXLfDJitACrqkt0gnOuSXsM3q0ufDVKnYyj21uw0=; b=u7Yst+9XAWecZRxlO6Kc5OenGthGAqW+lgJEav/wmyWxOePADKQHX3qhdwN/2DbwAx vbaD0MwKdHywG3FlYBqCy/pUULokrS6hb9OsoWUxmn9OuLssPknVJjzu2ZVTDtYKCmnp s2xAS/DwTaPEe35zSo0spA70/WsWdAfBBplWamtXQ6RDDHFdw40LYPvL6hlOc7iRKBXb k4kDrnai6FlJpG4J3K5War0lwPe7dEYJYMxWGZ46oEihhRrc7292+BHE+uV5GSPfLKAp oO9wNfNxONsKD5iN0DVaLZKKmqt0sfbySZCH39toaAL77spVLOyNGV4NhmR3RTxOhN4A I9QA== X-Received: by 10.180.206.171 with SMTP id lp11mr26527585wic.33.1413883371740; Tue, 21 Oct 2014 02:22:51 -0700 (PDT) Received: from topkick.lan (f052063137.adsl.alicedsl.de. [78.52.63.137]) by mx.google.com with ESMTPSA id fv2sm12476836wib.2.2014.10.21.02.22.49 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Oct 2014 02:22:50 -0700 (PDT) From: Sebastian Hesselbarth To: Sebastian Hesselbarth Cc: Chris Ball , Ulf Hansson , =?UTF-8?q?Antoine=20T=C3=A9nart?= , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND 02/12] mmc: sdhci-pxav3: Respect MMC_DDR52 timing on uhs signaling Date: Tue, 21 Oct 2014 11:22:34 +0200 Message-Id: <1413883364-681-3-git-send-email-sebastian.hesselbarth@gmail.com> In-Reply-To: <1413883364-681-1-git-send-email-sebastian.hesselbarth@gmail.com> References: <1413883364-681-1-git-send-email-sebastian.hesselbarth@gmail.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP commit bb8175a8aa42d731a840cd474e348ac3367eb5a0 ("mmc: sdhci: clarify DDR timing mode between SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR mode to be distinguished from SD-UHS. While the differentation may be useful, pxav3 SDHCI controller lacks a corresponding check in its custom .set_uhs_signaling callback for MMC_DDR52. This patch adds a new switch case for MMC_TIMING_MMC_DDR52 to MMC_TIMING_UHS_DDR50 case. Signed-off-by: Sebastian Hesselbarth --- Cc: Chris Ball Cc: Ulf Hansson Cc: "Antoine Ténart" Cc: linux-mmc@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/mmc/host/sdhci-pxav3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index 5036d7d39529..b55c807982fe 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -211,6 +211,7 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) case MMC_TIMING_UHS_SDR104: ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; break; + case MMC_TIMING_MMC_DDR52: case MMC_TIMING_UHS_DDR50: ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; break;