From patchwork Tue Oct 21 09:22:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sebastian Hesselbarth X-Patchwork-Id: 5112131 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D17A7C11AC for ; Tue, 21 Oct 2014 09:26:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EAC0920155 for ; Tue, 21 Oct 2014 09:26:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4452720136 for ; Tue, 21 Oct 2014 09:26:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754730AbaJUJZ7 (ORCPT ); Tue, 21 Oct 2014 05:25:59 -0400 Received: from mail-wi0-f180.google.com ([209.85.212.180]:61058 "EHLO mail-wi0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754664AbaJUJW4 (ORCPT ); Tue, 21 Oct 2014 05:22:56 -0400 Received: by mail-wi0-f180.google.com with SMTP id em10so1213257wid.13 for ; Tue, 21 Oct 2014 02:22:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; bh=IFaUhgBcbWxbof6JEWK+n+DH+acLQ6PQoxlKY0qG5lM=; b=c+Mk2RpilMEjF88PhzNQm8g44irtMWTAzQdH2cCq5UBZq3sBB28wtMve9kTLdeNI0Q Ys/t8JM/NKoFANg3WioAUNFWLXLXtH2fKN9zRhlbA0efqjOU/QXHhG+YG+pPWgVibqew X/QY7AfQdc+CEVEYwMTX27r+gAPjJxUa1LX1wStZRPyE8XE1nllKsXF5HfrgLKLdqfpP XjhpREvB7uDIGfAR5H0hQ4kyphWt2g7/HYflD3yJCD1gZI945IWFIsaz5wdJaOQ8eVwN b76mjWBLeYwENDMPdReAPn9TlPngmz+olyqalC1NikCdbtLlrX1+6OSfFztemVOQ+SSZ oTxg== X-Received: by 10.180.103.233 with SMTP id fz9mr26648340wib.80.1413883374439; Tue, 21 Oct 2014 02:22:54 -0700 (PDT) Received: from topkick.lan (f052063137.adsl.alicedsl.de. [78.52.63.137]) by mx.google.com with ESMTPSA id l10sm12435627wif.20.2014.10.21.02.22.52 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Oct 2014 02:22:53 -0700 (PDT) From: Sebastian Hesselbarth To: Sebastian Hesselbarth Cc: Chris Ball , Ulf Hansson , =?UTF-8?q?Antoine=20T=C3=A9nart?= , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND 08/12] mmc: sdhci-pxav3: Get optional core clock Date: Tue, 21 Oct 2014 11:22:40 +0200 Message-Id: <1413883364-681-9-git-send-email-sebastian.hesselbarth@gmail.com> In-Reply-To: <1413883364-681-1-git-send-email-sebastian.hesselbarth@gmail.com> References: <1413883364-681-1-git-send-email-sebastian.hesselbarth@gmail.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Besides the I/O clock, some PXAv3 SDHCI IP also requires a core clock to be enabled. Add an optional core clock to the corresponding driver. Signed-off-by: Sebastian Hesselbarth --- Cc: Chris Ball Cc: Ulf Hansson Cc: "Antoine Ténart" Cc: linux-mmc@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/mmc/host/sdhci-pxav3.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index 3dfd97977515..ad0badad0ebc 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -59,6 +59,7 @@ #define SDCE_MISC_INT_EN (1<<1) struct sdhci_pxa { + struct clk *clk_core; struct clk *clk_io; u8 power_mode; }; @@ -320,6 +321,10 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) pltfm_host->clk = pxa->clk_io; clk_prepare_enable(pxa->clk_io); + pxa->clk_core = devm_clk_get(dev, "core"); + if (!IS_ERR(pxa->clk_core)) + clk_prepare_enable(pxa->clk_core); + /* enable 1/8V DDR capable */ host->mmc->caps |= MMC_CAP_1_8V_DDR; @@ -392,6 +397,8 @@ err_add_host: err_of_parse: err_cd_req: clk_disable_unprepare(pxa->clk_io); + if (!IS_ERR(pxa->clk_core)) + clk_disable_unprepare(pxa->clk_core); err_clk_get: err_mbus_win: sdhci_pltfm_free(pdev); @@ -409,6 +416,8 @@ static int sdhci_pxav3_remove(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); clk_disable_unprepare(pxa->clk_io); + if (!IS_ERR(pxa->clk_core)) + clk_disable_unprepare(pxa->clk_core); sdhci_pltfm_free(pdev); @@ -456,6 +465,8 @@ static int sdhci_pxav3_runtime_suspend(struct device *dev) spin_unlock_irqrestore(&host->lock, flags); clk_disable_unprepare(pxa->clk_io); + if (!IS_ERR(pxa->clk_core)) + clk_disable_unprepare(pxa->clk_core); return 0; } @@ -468,6 +479,8 @@ static int sdhci_pxav3_runtime_resume(struct device *dev) unsigned long flags; clk_prepare_enable(pxa->clk_io); + if (!IS_ERR(pxa->clk_core)) + clk_prepare_enable(pxa->clk_core); spin_lock_irqsave(&host->lock, flags); host->runtime_suspended = false;