From patchwork Sun Feb 15 15:43:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Barry Song <21cnbao@gmail.com> X-Patchwork-Id: 5830281 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 50622BF440 for ; Sun, 15 Feb 2015 15:44:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A8A5F20219 for ; Sun, 15 Feb 2015 15:44:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E64E62017E for ; Sun, 15 Feb 2015 15:44:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754458AbbBOPoJ (ORCPT ); Sun, 15 Feb 2015 10:44:09 -0500 Received: from mail-wi0-f174.google.com ([209.85.212.174]:48412 "EHLO mail-wi0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751013AbbBOPoI (ORCPT ); Sun, 15 Feb 2015 10:44:08 -0500 Received: by mail-wi0-f174.google.com with SMTP id em10so21365050wid.1 for ; Sun, 15 Feb 2015 07:44:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=FFHOMjgMG433uvdb6vpeHjS6+0rZy83vk9uI9e+RJ4s=; b=UM1SfMn5BUUs5VzHrSf1reHeMVsVj/elvkRkwzp+S1qRysX7PNaqMZBKuAEN76JrTH r08+pB/qZbCSryiT/UEStL7AmzyZV/fRT881+TQ6uj0kNscaN4BnPak6KxZwHER9/lYg ulCxIDtsv8OnNkSZj+KH1/NypQMEUwSD3ZxSYTxJslEQsOVxF53M6kNw+iYVRPimdM17 oo1cHCcPSrKtmylEHFY1+MeeyFh2r3yO12GgypEpftZmg2Z+00a7dbpb1dOs69P3oPSz rYDWX7kevLZAI29UsxCgIZuCUIqq7/s4bTQ//sqTM74k21zywVH++jZVD3tRBBWnlWB8 iMaA== X-Received: by 10.180.93.226 with SMTP id cx2mr37092506wib.63.1424015046951; Sun, 15 Feb 2015 07:44:06 -0800 (PST) Received: from localhost.localdomain ([123.155.155.90]) by mx.google.com with ESMTPSA id mb20sm10898589wic.18.2015.02.15.07.44.00 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 15 Feb 2015 07:44:05 -0800 (PST) From: Barry Song <21cnbao@gmail.com> To: chris@printf.net, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, workgroup.linux@csr.com, weijun yang , Barry Song Subject: [PATCH] mmc: sirf: update sdhci_sirf_execute_tuning procedure Date: Sun, 15 Feb 2015 23:43:51 +0800 Message-Id: <1424015031-24676-1-git-send-email-21cnbao@gmail.com> X-Mailer: git-send-email 1.9.1 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: weijun yang For the original tuning code, delay value is set to SD Bus Clock Delay Register (SD_CLK_DELAY_SETTING) as (val | (Val << 7) | (val << 16)), which means CLK_DELAY_IN1, CLK_DELAY_IN2 and CLK_DELAY_OUT are the same and with 128 steps. This is doubtful. In CSR design specification documents CS-304575-DR-3H, this issue is clarified, the delay[13:0] in SD_CLK_DELAY_SETTING is simplied to the concatenation of {CLK_DELAY_IN2, CLK_DELAY_IN1}. Besides, for CMD19 tuning, no need to set CLK_DELAY_OUT([22,16] of SD_CLK_DELAY_SETTING). Signed-off-by: weijun yang Signed-off-by: Barry Song --- drivers/mmc/host/sdhci-sirf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c index f6f82ec..4331409 100644 --- a/drivers/mmc/host/sdhci-sirf.c +++ b/drivers/mmc/host/sdhci-sirf.c @@ -56,7 +56,7 @@ static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode) int tuning_seq_cnt = 3; u8 phase, tuned_phases[SIRF_TUNING_COUNT]; u8 tuned_phase_cnt = 0; - int rc, longest_range = 0; + int rc = 0, longest_range = 0; int start = -1, end = 0, tuning_value = -1, range = 0; u16 clock_setting; struct mmc_host *mmc = host->mmc; @@ -68,7 +68,7 @@ retry: phase = 0; do { sdhci_writel(host, - clock_setting | phase | (phase << 7) | (phase << 16), + clock_setting | phase, SDHCI_CLK_DELAY_SETTING); if (!mmc_send_tuning(mmc)) { @@ -102,7 +102,7 @@ retry: */ phase = tuning_value; sdhci_writel(host, - clock_setting | phase | (phase << 7) | (phase << 16), + clock_setting | phase, SDHCI_CLK_DELAY_SETTING); dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",