From patchwork Wed Mar 18 11:20:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 6038281 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 65227BF90F for ; Wed, 18 Mar 2015 11:16:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C0819204A9 for ; Wed, 18 Mar 2015 11:16:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4611B204EC for ; Wed, 18 Mar 2015 11:16:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755641AbbCRLQs (ORCPT ); Wed, 18 Mar 2015 07:16:48 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:8361 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755704AbbCRLQp (ORCPT ); Wed, 18 Mar 2015 07:16:45 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NLE00C4XNBV3E90@mailout3.samsung.com>; Wed, 18 Mar 2015 20:16:43 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.51]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 4C.B3.11124.B9E59055; Wed, 18 Mar 2015 20:16:43 +0900 (KST) X-AuditID: cbfee68e-f79b46d000002b74-ba-55095e9b8b21 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 5F.6A.09430.B9E59055; Wed, 18 Mar 2015 20:16:43 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NLE008TVNB61110@mmp2.samsung.com>; Wed, 18 Mar 2015 20:16:42 +0900 (KST) From: Alim Akhtar To: kgene@kernel.org Cc: linux-mmc@vger.kernel.org, ulf.hansson@linaro.org, jh80.chung@samsung.com, tgih.jun@samsung.com, dianders@chromium.org, alim.akhtar@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, a.kesavan@samsung.com, alim.akhtar@samsung.com, javier@dowhile0.org Subject: [PATCH v7] ARM: dts: Add HS400 support for exynos5420 and exynos5800 Date: Wed, 18 Mar 2015 16:50:23 +0530 Message-id: <1426677623-30532-1-git-send-email-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.2.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNLMWRmVeSWpSXmKPExsVy+t8zY93ZcZyhBideSFk8XrOYyWLprWqL B/O2sVnMP3KO1eLssoNsFtd+z2CzuPGrjdWi//FrZotNj6+xWhz5389oMeP8PiaLD/cvMlsc XxvuwOsxu+Eii8ff2a3MHjtn3WX32LSqk83jzrU9bB6bl9R79G1ZxejxeZNcAEcUl01Kak5m WWqRvl0CV8auObEFd+Qqej+tZWpg/CDZxcjBISFgIvF0UXAXIyeQKSZx4d56ti5GLg4hgWWM EjtvzmeDSJhIrDs1nxUiMZ1RYsWHg0wQzgQmiS0NX1lAqtgEtCXuTt/CBDJVREBEYvYFLpAa ZoHDTBL7j21kBakRFvCVWHl3JStIDYuAqsTii9wgYV4Bd4n+IztZIJbJSWy59YgdpFdCYB+7 xKv1MxhBEiwCAhLfJh9igbhaVmLTAWaIekmJgytusExgFFzAyLCKUTS1ILmgOCm9yEivODG3 uDQvXS85P3cTIyQO+nYw3jxgfYhRgINRiYdX4ipHqBBrYllxZe4hRlOgDROZpUST84HRllcS b2hsZmRhamJqbGRuaaYkzpsg9TNYSCA9sSQ1OzW1ILUovqg0J7X4ECMTB6dUA2PAn+NFGtPd TbveLfj6lI1p+icmz9dv9Wc0XWw405S1baFM1wXtH7cbGyNjGU4rzBIV/PFM5eCKA1zZrZVM y8s/8Zr3LKxQcG7N3B9W8NXHymmWtyZv96p9CTXNTXI307Ql9e8Urtj4e2rGKZkvAgy+Trrl 8fdKDirerc0QCtj4munf6RMdr5VYijMSDbWYi4oTAZYZwb9+AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrGIsWRmVeSWpSXmKPExsVy+t9jQd3ZcZyhBguuCFs8XrOYyWLprWqL B/O2sVnMP3KO1eLssoNsFtd+z2CzuPGrjdWi//FrZotNj6+xWhz5389oMeP8PiaLD/cvMlsc XxvuwOsxu+Eii8ff2a3MHjtn3WX32LSqk83jzrU9bB6bl9R79G1ZxejxeZNcAEdUA6NNRmpi SmqRQmpecn5KZl66rZJ3cLxzvKmZgaGuoaWFuZJCXmJuqq2Si0+ArltmDtDFSgpliTmlQKGA xOJiJX07TBNCQ9x0LWAaI3R9Q4LgeowM0EDCOsaMXXNiC+7IVfR+WsvUwPhBsouRk0NCwERi 3an5rBC2mMSFe+vZuhi5OIQEpjNKrPhwkAnCmcAksaXhKwtIFZuAtsTd6VuAEhwcIgIiErMv cIHUMAscZpLYf2wj2CRhAV+JlXdXsoLUsAioSiy+yA0S5hVwl+g/spMFYpmcxJZbj9gnMHIv YGRYxSiaWpBcUJyUnmukV5yYW1yal66XnJ+7iREcZ8+kdzCuarA4xCjAwajEwytxlSNUiDWx rLgy9xCjBAezkgjvvnDOUCHelMTKqtSi/Pii0pzU4kOMpkDLJzJLiSbnA1NAXkm8obGJmZGl kZmFkYm5uZI4r5J9W4iQQHpiSWp2ampBahFMHxMHp1QDY1XBRAfLxbmdYs33Q8KXZj7xtW/4 1R35/fDuVFO5NTfbWi54r28zEMr+3539PH01+1mn3w4zl26SXWy1gYW9zWtj7MbdvqpHtERs SspvHVB7oZi7/M7/GbvsUu1s9yt2/ryUYfhw7dTV5xXr+8VfzIrc8dGFIUNrjcm/N0lTFgQL f0h64CMQpsRSnJFoqMVcVJwIAD5uYhbJAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Seungwon Jeon HS400 timing values are added for SMDK5420, exynos5420-peach-pit and exynos5800-peach-pi boards. This also adds RCLK GPIO line, this gpio should be in pull-down state. This also enables HS400 on peach-pi and this updates the clock frequency to 800MHz to be set as input clock to controller. Signed-off-by: Seungwon Jeon Signed-off-by: Alim Akhtar [Alim: addressed review comments] Acked-by: Jaehoon Chung --- Changes in V7: Add back bus1 pin, which was removed during rebase in v6 as rightly pointed out by Javier[1]. Changes in V6: Rebased on kukjin's for-next branch[0] (commit: 77105c8 Merge branch 'v4.0-samsung-fixes-2' into for-next) [0]: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [1]: http://www.spinics.net/lists/arm-kernel/msg406618.html arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +++- arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 7 +++++++ arch/arm/boot/dts/exynos5420-smdk5420.dts | 5 ++++- arch/arm/boot/dts/exynos5800-peach-pi.dts | 7 +++++-- 4 files changed, 19 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 3f4e2fe..0788d08 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -699,8 +699,10 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; bus-width = <8>; }; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index ba686e4..8b15316 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -201,6 +201,13 @@ samsung,pin-drv = <3>; }; + sd0_rclk: sd0-rclk { + samsung,pins = "gpc0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + sd1_cmd: sd1-cmd { samsung,pins = "gpc1-1"; samsung,pin-function = <2>; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 7a56852..9103f23 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -80,8 +80,11 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 + &sd0_rclk>; bus-width = <8>; cap-mmc-highspeed; }; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index c833bac..412f41d 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -654,15 +654,18 @@ num-slots = <1>; broken-cd; mmc-hs200-1_8v; + mmc-hs400-1_8v; cap-mmc-highspeed; non-removable; card-detect-delay = <200>; - clock-frequency = <400000000>; + clock-frequency = <800000000>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; bus-width = <8>; };