From patchwork Sun Oct 4 12:04:12 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Barry Song <21cnbao@gmail.com> X-Patchwork-Id: 7323541 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C6FD8BEEA4 for ; Sun, 4 Oct 2015 11:55:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F3FD420456 for ; Sun, 4 Oct 2015 11:55:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0709E203FB for ; Sun, 4 Oct 2015 11:55:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751436AbbJDLzu (ORCPT ); Sun, 4 Oct 2015 07:55:50 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:33260 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751352AbbJDLzt (ORCPT ); Sun, 4 Oct 2015 07:55:49 -0400 Received: by pacex6 with SMTP id ex6so148928104pac.0 for ; Sun, 04 Oct 2015 04:55:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zkZzWCq2YJL15s9PW1OB4TzZJjHlpNFrqXnnXc29PJM=; b=hjDU4M4efWXnG6wj5VwgMdjnUrVCkOJOZSjinDtPOD8hxlCtMWEAu/gaZ1JukLFgD4 X97yVrW5O9+kaKNbIH7z10Ui8w0AKeVnSjynI8U9xepFpJKEQ1MoAt+yDFdjakQg/HjT Zr74H/1xgCjhClq1MC/moHMqzEHSxwpsbVXl+58ga4QN6YI1PL4y3KFu3oK3qVUq8Kbu S0yG6gFJaB2NE1OogKVy74a9pipk0hbooocmAyVyxogaO4EVvWVxY/A8a7d4sg8/4W3/ A7S8WTPaNiBXOiiQNUF8KV5KLCcH4tkjLLaY1rSPtLYzS2Ljl9VDfvqFV/9uhGfA7Q1T Ie3g== X-Received: by 10.66.229.67 with SMTP id so3mr33362054pac.66.1443959749389; Sun, 04 Oct 2015 04:55:49 -0700 (PDT) Received: from ip-172-31-29-47.ap-northeast-1.compute.internal (ec2-54-65-106-64.ap-northeast-1.compute.amazonaws.com. [54.65.106.64]) by smtp.gmail.com with ESMTPSA id gd2sm21803392pbb.41.2015.10.04.04.55.46 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 04 Oct 2015 04:55:47 -0700 (PDT) From: Barry Song <21cnbao@gmail.com> To: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org Cc: workgroup.linux@csr.com, Weijun Yang , Barry Song Subject: [PATCH v3 2/3] mmc: sdhci: enable tuning for DDR50 Date: Sun, 4 Oct 2015 12:04:12 +0000 Message-Id: <1443960253-4082-2-git-send-email-21cnbao@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1443960253-4082-1-git-send-email-21cnbao@gmail.com> References: <1443960253-4082-1-git-send-email-21cnbao@gmail.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Weijun Yang CMD19 tuning is also available for DDR50 mode. Signed-off-by: Weijun Yang Signed-off-by: Barry Song --- drivers/mmc/host/sdhci.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 64b7fdb..2ea30fa 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1893,9 +1893,9 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) tuning_count = host->tuning_count; /* - * The Host Controller needs tuning only in case of SDR104 mode - * and for SDR50 mode when Use Tuning for SDR50 is set in the - * Capabilities register. + * The Host Controller needs tuning in case of SDR104 and DDR5 + * mode, and for SDR50 mode when Use Tuning for SDR50 is set in + * the Capabilities register. * If the Host Controller supports the HS200 mode then the * tuning function has to be executed. */ @@ -1915,6 +1915,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) break; case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_UHS_DDR50: break; case MMC_TIMING_UHS_SDR50: