From patchwork Tue Oct 6 01:22:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Wojtas X-Patchwork-Id: 7332981 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D322FBEEA4 for ; Tue, 6 Oct 2015 01:19:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 049E42069D for ; Tue, 6 Oct 2015 01:19:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1FC8A2068E for ; Tue, 6 Oct 2015 01:19:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751448AbbJFBQS (ORCPT ); Mon, 5 Oct 2015 21:16:18 -0400 Received: from mail-lb0-f175.google.com ([209.85.217.175]:36747 "EHLO mail-lb0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751441AbbJFBPz (ORCPT ); Mon, 5 Oct 2015 21:15:55 -0400 Received: by lbcao8 with SMTP id ao8so67663089lbc.3 for ; Mon, 05 Oct 2015 18:15:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tHXocJza6JlbPA7QCWR4F4gbHGv5ejjauxttqwKH58M=; b=Vyh7OTCyUTp7uvn9HWdWz9PA/ZQmoR6QdZUYm4Zb8asxlTJ1WVPSqJ1GQh3qwjipyq TUD39GUESIFDaaSXMDs+9ld+94ECbIuSAy53UKVZkBqswRDvJawKCwPIuvxBC9XTejPV b5VMU26ro22ci7jv+uSi5gqA6rYIZkfBeUknGOjv2oZGn1NvzhQ3a2FT/oXtLL2u5rIm lkYmHQzoHL+i0rVvc0j+B1I1vbMxWVWi4twu6Lo+SvDXrf/dUrjcm0qt/343hc7n3NFy 4Am4oadCh2VtDEmubrmYNmkCcUyKVcYQ6DzAd9Rg9BIvfOlQ6fvgXD0r3CqbT050hip0 93VQ== X-Gm-Message-State: ALoCoQkB3MDh54V+Ricb6cirjEVs9NmKmsfxAL3H9QnrEEOcyOX23oN1LodF/OidtpE6vQawhFZx X-Received: by 10.112.184.137 with SMTP id eu9mr13048720lbc.21.1444094154578; Mon, 05 Oct 2015 18:15:54 -0700 (PDT) Received: from enkidu.semihalf.local (cardhu.semihalf.com. [213.17.239.108]) by smtp.gmail.com with ESMTPSA id x1sm4694780lbb.32.2015.10.05.18.15.52 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Oct 2015 18:15:53 -0700 (PDT) From: Marcin Wojtas To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org Cc: ulf.hansson@linaro.org, sebastian.hesselbarth@gmail.com, andrew@lunn.ch, jason@lakedaemon.net, thomas.petazzoni@free-electrons.com, gregory.clement@free-electrons.com, nadavh@marvell.com, alior@marvell.com, tawfik@marvell.com, mw@semihalf.com, jaz@semihalf.com, Subject: [PATCH 2/8] mmc: sdhci-pxav3: disable clock inversion for HS MMC cards Date: Tue, 6 Oct 2015 03:22:36 +0200 Message-Id: <1444094562-31165-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1444094562-31165-1-git-send-email-mw@semihalf.com> References: <1444094562-31165-1-git-send-email-mw@semihalf.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Nadav Haklai According to 'FE-2946959' erratum the clock inversion option is needed to support slow frequencies when the card input hold time requirement is high. This setting is not required for high speed MMC and might cause timing violation. Signed-off-by: Nadav Haklai Cc: # v4.2 Reviewed-by: Gregory CLEMENT --- drivers/mmc/host/sdhci-pxav3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index 976cddd..89a9e49 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -291,6 +291,9 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) uhs == MMC_TIMING_UHS_DDR50) { reg_val &= ~SDIO3_CONF_CLK_INV; reg_val |= SDIO3_CONF_SD_FB_CLK; + } else if (uhs == MMC_TIMING_MMC_HS) { + reg_val &= ~SDIO3_CONF_CLK_INV; + reg_val &= ~SDIO3_CONF_SD_FB_CLK; } else { reg_val |= SDIO3_CONF_CLK_INV; reg_val &= ~SDIO3_CONF_SD_FB_CLK;