From patchwork Tue Oct 13 09:37:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chaotian Jing X-Patchwork-Id: 7382301 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C3D8C9F1D5 for ; Tue, 13 Oct 2015 09:39:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F29512096A for ; Tue, 13 Oct 2015 09:39:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0334D20964 for ; Tue, 13 Oct 2015 09:39:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932085AbbJMJie (ORCPT ); Tue, 13 Oct 2015 05:38:34 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:48042 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752704AbbJMJia (ORCPT ); Tue, 13 Oct 2015 05:38:30 -0400 X-Listener-Flag: 11101 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2123391692; Tue, 13 Oct 2015 17:38:28 +0800 Received: from mhfsdcap03.localdomain (10.17.3.153) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Tue, 13 Oct 2015 17:38:26 +0800 From: Chaotian Jing To: Ulf Hansson CC: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Matthias Brugger , Catalin Marinas , Will Deacon , Hans de Goede , Lars-Peter Clausen , Javier Martinez Canillas , Sascha Hauer , Howard Chen , Daniel Kurtz , Adrian Hunter , Kristina Martsenko , Sergei Shtylyov , , , , , , , Chaotian Jing Subject: [PATCH 4/4] arm64: dts: mediatek:: Add HS200/HS400/SDR50/SDR104 support Date: Tue, 13 Oct 2015 17:37:58 +0800 Message-ID: <1444729078-26585-5-git-send-email-chaotian.jing@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1444729078-26585-1-git-send-email-chaotian.jing@mediatek.com> References: <1444729078-26585-1-git-send-email-chaotian.jing@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add HS200/HS400 support for EMMC Add SDR50/SDR104 support for SD Add 400Mhz source clock Signed-off-by: Chaotian Jing --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 21 ++++++++++++++++----- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 5 +++-- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 4be66ca..123dc82 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -70,8 +70,12 @@ pinctrl-0 = <&mmc0_pins_default>; pinctrl-1 = <&mmc0_pins_uhs>; bus-width = <8>; - max-frequency = <50000000>; + max-frequency = <200000000>; cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + hs400-ds-delay = <0x14015>; vmmc-supply = <&mt6397_vemc_3v3_reg>; vqmmc-supply = <&mt6397_vio18_reg>; non-removable; @@ -83,9 +87,10 @@ pinctrl-0 = <&mmc1_pins_default>; pinctrl-1 = <&mmc1_pins_uhs>; bus-width = <4>; - max-frequency = <50000000>; + max-frequency = <200000000>; cap-sd-highspeed; - sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; cd-gpios = <&pio 132 0>; vmmc-supply = <&mt6397_vmch_reg>; vqmmc-supply = <&mt6397_vmc_reg>; @@ -154,13 +159,19 @@ , ; input-enable; - drive-strength = ; + drive-strength = ; bias-pull-up = ; }; pins_clk { pinmux = ; - drive-strength = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins_ds { + pinmux = ; + drive-strength = ; bias-pull-down = ; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index d18ee42..3b03d7e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -450,8 +450,9 @@ reg = <0 0x11230000 0 0x1000>; interrupts = ; clocks = <&pericfg CLK_PERI_MSDC30_0>, - <&topckgen CLK_TOP_MSDC50_0_H_SEL>; - clock-names = "source", "hclk"; + <&topckgen CLK_TOP_MSDC50_0_H_SEL>, + <&topckgen CLK_TOP_MSDCPLL_D2>; + clock-names = "source", "hclk", "400mhz"; status = "disabled"; };