From patchwork Thu Oct 15 16:25:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Wojtas X-Patchwork-Id: 7407971 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0040FBEEA4 for ; Thu, 15 Oct 2015 16:18:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2655920817 for ; Thu, 15 Oct 2015 16:18:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 35EFB20664 for ; Thu, 15 Oct 2015 16:18:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753870AbbJOQSt (ORCPT ); Thu, 15 Oct 2015 12:18:49 -0400 Received: from mail-lb0-f171.google.com ([209.85.217.171]:33835 "EHLO mail-lb0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753747AbbJOQR5 (ORCPT ); Thu, 15 Oct 2015 12:17:57 -0400 Received: by lbbwb3 with SMTP id wb3so13273799lbb.1 for ; Thu, 15 Oct 2015 09:17:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K924LoV2/t8ILz1pKBXfHLk1ZaQTfwQQ2yyllIa160Q=; b=acXvMFKmz83a/QkgdI7xbsS8P4203XoWp+wElkcCe1ULhISXgC4/GzB0MqrChJFHza 4FIQ9AAHrGC+NG+/2hdhpNxw7fd+e1xbOoVKWjdIGz/ckDeVbIdXqjtVAdMJzQsypTrL RmdL+UlHKpMWAHLb7VaKHFVMK4UwZcw8n6btmz5Nm7BRp5sCbwNL6SBxk/OWjD8o5AxQ xG+bG9DnsV9qJg2S/Xe8mUOjHupQtbTcaKn3UsI6ZmIspD6w1tqZhOr9Hf385OP1ZYGu Qe6jaJmdeKAlo8AWzJTLk6uWmhc48QBbcsd6C+2uXau2wdyhZkE47OZCUOYQXG3G/1QF Ydfg== X-Gm-Message-State: ALoCoQmBV7bswyzq1jE4WgnJGvdeXkM/fK8L2u0KORCjff8Vv+yLV/bOw0oZ+LYE6pnMsG9re+b+ X-Received: by 10.112.150.201 with SMTP id uk9mr5168056lbb.102.1444925875772; Thu, 15 Oct 2015 09:17:55 -0700 (PDT) Received: from enkidu.semihalf.local ([80.82.22.190]) by smtp.gmail.com with ESMTPSA id r137sm2185323lfe.34.2015.10.15.09.17.54 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Oct 2015 09:17:55 -0700 (PDT) From: Marcin Wojtas To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org Cc: ulf.hansson@linaro.org, sebastian.hesselbarth@gmail.com, andrew@lunn.ch, jason@lakedaemon.net, thomas.petazzoni@free-electrons.com, gregory.clement@free-electrons.com, nadavh@marvell.com, alior@marvell.com, tawfik@marvell.com, mw@semihalf.com, jaz@semihalf.com, jszhang@marvell.com Subject: [PATCH v3 5/5] mmc: sdhci-pxav3: enable modifying MMC_CARD bit during card initialization Date: Thu, 15 Oct 2015 18:25:46 +0200 Message-Id: <1444926346-29763-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1444926346-29763-1-git-send-email-mw@semihalf.com> References: <1444926346-29763-1-git-send-email-mw@semihalf.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Marvell Armada 38x SoC's the MMC_CARD bit in SD_CE_ATA_1 register must be set to 0x1 when a MMC card is supposed to work in DDR mode, or when commands CMD11, CMD14 and CMD20 are used. This commit enables the above for all MMC cards by modifying the host registers during card initialization. It is done by using init_card() callback with pxa->mbus_win_regs as a flag, which notifies if Armada 38x controller is in use. Signed-off-by: Marcin Wojtas --- drivers/mmc/host/sdhci-pxav3.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index d813233..8742afd 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -57,6 +57,7 @@ #define SD_SPI_MODE 0x108 #define SD_CE_ATA_1 0x10C +#define SDCE_MMC_CARD BIT(28) #define SD_CE_ATA_2 0x10E #define SDCE_MISC_INT (1<<2) @@ -230,6 +231,26 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask) } } +static void pxav3_init_card(struct sdhci_host *host, struct mmc_card *card) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_pxa *pxa = pltfm_host->priv; + u32 reg_val; + + /* + * Armada 38x SDHCI controller requires update of + * MMC_CARD bit depending on inserted card type. + */ + if (pxa->mbus_win_regs) { + reg_val = sdhci_readl(host, SD_CE_ATA_1); + if (mmc_card_mmc(card)) + reg_val |= SDCE_MMC_CARD; + else + reg_val &= ~SDCE_MMC_CARD; + sdhci_writel(host, reg_val, SD_CE_ATA_1); + } +} + #define MAX_WAIT_COUNT 5 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode) { @@ -347,6 +368,7 @@ static const struct sdhci_ops pxav3_sdhci_ops = { .set_bus_width = sdhci_set_bus_width, .reset = pxav3_reset, .set_uhs_signaling = pxav3_set_uhs_signaling, + .init_card = pxav3_init_card, }; static struct sdhci_pltfm_data sdhci_pxav3_pdata = {