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Fri, 15 Apr 2016 17:38:14 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id u3FHb2HY019919; Fri, 15 Apr 2016 10:38:11 -0700 From: Dong Aisheng To: CC: , , , , , , , Subject: [PATCH 23/23] mmc: sdhci-esdhc-imx: clear tuning bits during hwinit Date: Sat, 16 Apr 2016 01:29:47 +0800 Message-ID: <1460741387-23815-24-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1460741387-23815-1-git-send-email-aisheng.dong@nxp.com> References: <1460741387-23815-1-git-send-email-aisheng.dong@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131052154952040702; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.158.2; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(1110001)(1109001)(339900001)(199003)(189002)(105606002)(5003940100001)(47776003)(48376002)(2906002)(77096005)(110136002)(36756003)(33646002)(76176999)(189998001)(230783001)(50986999)(106466001)(50466002)(87936001)(2950100001)(2351001)(229853001)(19580395003)(19580405001)(50226001)(1220700001)(1096002)(81166005)(85426001)(6806005)(586003)(5008740100001)(4326007)(11100500001)(86362001)(92566002)(104016004)(7059030); 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DM2PR0301MB1229; 5:vYts2btldtGVxIExjPxaTSdPj7BNjcEtw5JOhnZjb2CtYdZdXtwBUfBUWOrCwt5tn9sjHjXpuWOyEgPgtvgVjoaFzW/lnHTbZ2DZRSsIfVBvoPRjl3UV9M+x9kwTmQ1Ee/id/tUuF+KDX2uSh9lKBlT7JzulNLlHrGd21GWW0JM=; 24:THjPNFfmRaA8WJKMqVXd4zEh8Ju+mEtiLQb9v711q4ZywrjYT1XtTDqjzt1X2jXWaN2fSOzE02OlxwAqDAWG0ZZ3n17/BNO0riUYwLHvWwI= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2016 17:38:14.9544 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0301MB1229 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The tuning bits like FBCLK_SEL, SMP_CLK_SEL and DLY_CELL which affects timing may have already been set by ROM if booting from SD3.0 mode like SDR104. Let's clear it first during hw initialization before do the new card enumeration. For system resume case, it's safe to clear them too since the following card re-initialization in mmc_xx_init_card() will do retuning and set correct value again. Signed-off-by: Dong Aisheng Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-esdhc-imx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 98aa6b5..6a699d1 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -1018,6 +1018,11 @@ static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) } writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); } + + /* clear tuning bits in case ROM has set it already */ + writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); + writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR); + writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); } }