From patchwork Wed May 4 01:43:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 9008991 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id EA2F49F372 for ; Wed, 4 May 2016 01:44:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0880E2037E for ; Wed, 4 May 2016 01:44:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C221320374 for ; Wed, 4 May 2016 01:43:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756337AbcEDBn6 (ORCPT ); Tue, 3 May 2016 21:43:58 -0400 Received: from lucky1.263xmail.com ([211.157.147.131]:44029 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756112AbcEDBn5 (ORCPT ); Tue, 3 May 2016 21:43:57 -0400 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.84]) by lucky1.263xmail.com (Postfix) with SMTP id 5B6558E362; Wed, 4 May 2016 09:43:50 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-KSVirus-check: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id DD2392183E; Wed, 4 May 2016 09:43:46 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: adrian.hunter@intel.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <67d1ffe85c7c73beff40e16c48bf52ba> X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 5616L1L9KR; Wed, 04 May 2016 09:43:47 +0800 (CST) From: Shawn Lin To: Adrian Hunter , Ulf Hansson Cc: Michal Simek , soren.brinkmann@xilinx.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Doug Anderson , Heiko Stuebner , linux-rockchip@lists.infradead.org, Shawn Lin Subject: [PATCH v3] mmc: sdhci-of-arasan: fix set_clock when a phy is supported Date: Wed, 4 May 2016 09:43:24 +0800 Message-Id: <1462326204-5090-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.8.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY, URIBL_BLACK autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP commit 61b914eb81f8 ("mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan") introduce phy support for arasan. According to the vendor's databook, we should make sure the phy is in poweroff status before we configure the clk stuff. Otherwise it may cause some IO sample timing issues from the test. And we don't need this extra operation while running in low performance mode since phy doesn't trigger sampling block. Signed-off-by: Shawn Lin Acked-by: Adrian Hunter --- Changes in v3: - avoid use sleep function with the scope of spinlock because phy APIs call mutex. Changes in v2: - Rename commit msg title to indicate it's a fix drivers/mmc/host/sdhci-of-arasan.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 2e482b1..b6f4c1d 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -55,8 +55,32 @@ static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host) return freq; } +static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); + bool ctrl_phy = false; + + if (clock > MMC_HIGH_52_MAX_DTR && (!IS_ERR(sdhci_arasan->phy))) + ctrl_phy = true; + + if (ctrl_phy) { + spin_unlock_irq(&host->lock); + phy_power_off(sdhci_arasan->phy); + spin_lock_irq(&host->lock); + } + + sdhci_set_clock(host, clock); + + if (ctrl_phy) { + spin_unlock_irq(&host->lock); + phy_power_on(sdhci_arasan->phy); + spin_lock_irq(&host->lock); + } +} + static struct sdhci_ops sdhci_arasan_ops = { - .set_clock = sdhci_set_clock, + .set_clock = sdhci_arasan_set_clock, .get_max_clock = sdhci_pltfm_clk_get_max_clock, .get_timeout_clock = sdhci_arasan_get_timeout_clock, .set_bus_width = sdhci_set_bus_width,