From patchwork Tue Jun 7 22:44:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9162775 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4DEE960467 for ; Tue, 7 Jun 2016 22:48:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3EF7428369 for ; Tue, 7 Jun 2016 22:48:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 334F728370; Tue, 7 Jun 2016 22:48:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D51F628369 for ; Tue, 7 Jun 2016 22:48:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423664AbcFGWsl (ORCPT ); Tue, 7 Jun 2016 18:48:41 -0400 Received: from mail-pf0-f174.google.com ([209.85.192.174]:35158 "EHLO mail-pf0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423468AbcFGWpK (ORCPT ); Tue, 7 Jun 2016 18:45:10 -0400 Received: by mail-pf0-f174.google.com with SMTP id c2so9268782pfa.2 for ; Tue, 07 Jun 2016 15:45:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KjNkX2Sc+gBVd3v74A0J6IpVpDHf2qxF7Yp6OXD8uDQ=; b=MXcZsm7smXmS2+X0ohAJJtVGOsNsgcZ+NGqGDO2iPRzL/7lc6gG99Fh9BqQrjM5M+W D2nIqJnLUa32r75HNKzq6T8XJ2EMLuDYEZAlWbQFIun5IhCgZU2Af3lI7ehxpDmgihZP HIVWX95cfANk2n2esb1/zRncBAq/HJLWm8JXc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KjNkX2Sc+gBVd3v74A0J6IpVpDHf2qxF7Yp6OXD8uDQ=; b=lq+Sp/O7z0/qY7LRkV8g9BFxeUfNBpatObuBNRmgniaJL8roXcB0Di9p/zSUi079/k Cwhe/ShcolbofB7xRBWFQ7BGnvbu+Tu7wJINdoixqsTcEw8BVdPZDWvL3bzr/0gFm+6H bBz5F/Cf8zb9i7g8IJqM1EL/mL5TymL9atya03IzSUaMzATajC+3KBkdU1pVGBSbAv3W 3of7K1R1qDtAgcrIqu8fNFGhOVXYKIrRbZnXXljy/kKuR/1SbW/my14XIbN60vmIIQhO lFX2tvScDzeQtRaU4kiYH59CwXIgt8qUW9muQ+plJnwdUXTCPiXqv2mRgmFONCtTLDc3 gPhA== X-Gm-Message-State: ALyK8tJSC0DRwfxhCbk0aMvfTg9YcHFWmwq7Xw3l8wH03jlIai2pr6YuHnnu/tz5mwkVlGYV X-Received: by 10.98.4.195 with SMTP id 186mr1925343pfe.98.1465339509535; Tue, 07 Jun 2016 15:45:09 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id 4sm37641782pfm.15.2016.06.07.15.45.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Jun 2016 15:45:09 -0700 (PDT) From: Douglas Anderson To: ulf.hansson@linaro.org, kishon@ti.com, Heiko Stuebner , robh+dt@kernel.org Cc: shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Douglas Anderson , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 01/11] phy: rockchip-emmc: Increase lock time allowance Date: Tue, 7 Jun 2016 15:44:34 -0700 Message-Id: <1465339484-969-2-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1465339484-969-1-git-send-email-dianders@chromium.org> References: <1465339484-969-1-git-send-email-dianders@chromium.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Previous PHY code waited a fixed amount of time for the DLL to lock at power on time. Unfortunately, the time for the DLL to lock is actually a bit more dynamic and can be longer if the card clock is slower. Instead of waiting a fixed 30 us, let's now dynamically wait until the lock bit gets set. We'll wait up to 10 ms which should be OK even if the card clock is at the super slow 100 kHz. On its own, this change makes the PHY power on code a little more robust. Before this change the PHY was relying on the eMMC code to make sure the PHY was only powered on when the card clock was set to at least 50 MHz before, though this reliance wasn't documented anywhere. This change will be even more useful in future changes where we actually need to be able to wait for a DLL lock at slower clock speeds. Signed-off-by: Douglas Anderson --- drivers/phy/phy-rockchip-emmc.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c index a69f53630e67..8336053aea5c 100644 --- a/drivers/phy/phy-rockchip-emmc.c +++ b/drivers/phy/phy-rockchip-emmc.c @@ -85,6 +85,7 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy, { unsigned int caldone; unsigned int dllrdy; + unsigned long timeout; /* * Keep phyctrl_pdb and phyctrl_endll low to allow @@ -137,15 +138,25 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy, PHYCTRL_ENDLL_MASK, PHYCTRL_ENDLL_SHIFT)); /* - * After enable analog DLL circuits, we need an extra 10.2us - * for dll to be ready for work. But according to testing, we - * find some chips need more than 25us. + * After enabling analog DLL circuits docs say that we need 10.2 us if + * our source clock is at 50 MHz and that lock time scales linearly + * with clock speed. If we are powering on the PHY and the card clock + * is super slow (like 100 kHZ) this could take as long as 5.1 ms. + * Hopefully we won't be running at 100 kHz, but we should still make + * sure we wait long enough. */ - udelay(30); - regmap_read(rk_phy->reg_base, - rk_phy->reg_offset + GRF_EMMCPHY_STATUS, - &dllrdy); - dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; + timeout = jiffies + msecs_to_jiffies(10); + do { + udelay(1); + + regmap_read(rk_phy->reg_base, + rk_phy->reg_offset + GRF_EMMCPHY_STATUS, + &dllrdy); + dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; + if (dllrdy == PHYCTRL_DLLRDY_DONE) + break; + } while (!time_after(jiffies, timeout)); + if (dllrdy != PHYCTRL_DLLRDY_DONE) { pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n"); return -ETIMEDOUT;