From patchwork Tue Jun 7 22:44:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9162751 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 000DD60832 for ; Tue, 7 Jun 2016 22:47:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E3BF128360 for ; Tue, 7 Jun 2016 22:47:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CA65F2836E; Tue, 7 Jun 2016 22:47:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7378A28360 for ; Tue, 7 Jun 2016 22:47:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753988AbcFGWrf (ORCPT ); Tue, 7 Jun 2016 18:47:35 -0400 Received: from mail-pf0-f171.google.com ([209.85.192.171]:36514 "EHLO mail-pf0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423506AbcFGWpR (ORCPT ); Tue, 7 Jun 2016 18:45:17 -0400 Received: by mail-pf0-f171.google.com with SMTP id t190so8176475pfb.3 for ; Tue, 07 Jun 2016 15:45:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HfTOsqgh8K4SEOetO/426fupm56oR2de0bwA6m39Cvk=; b=VXVyXXUp17z+ZzI0MYbi7MN0ma9Vs8xYCfQhBP/o6nfj5TP09uYx9ZSrO9lCR5/aNU RtPlWP+8Qj9HhsNKOTEr14ENiYM7uyTMiI1EKRbPKtbWKEVgIF4AwlvRLbNhE2+s2Isx dmwENaeR2HdNxYRGcZyfNh4peq6KEU9SXTyOo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HfTOsqgh8K4SEOetO/426fupm56oR2de0bwA6m39Cvk=; b=GpDkr9AOdxqqkIuyvP2g+RpGeqyo1Ir3ZPV9u0AW1/TBP6SXWtNesCEAhv6ZHY/kUc Juq3ibtagHPtr22v5fz/aqhZ3PcmQ/gMhsMDrlknmDQrBr/7DBsbxY1oO2jzhYKYaFbC DcCYWAfuUk72hX1+vvfMQQB/ykLNvb/Ux9i6AUdD8vwF1WLjT/Fpb8rvKUsK9bxC+VwF nysmAjzgF196LzPdLPnkUuxY0M0BoNZqThQWKAAEoRUJDxlyoAcb1rc609B1kcCN7rVj ilc0pWSI9Cd3FOIAzR5vVpzOJnxYFBmR135HL2o3BP/2/SjOjkgGi0zKPKTcGrLsFmQ3 G1fA== X-Gm-Message-State: ALyK8tL6aJAExWKJx8qBtEyxnfjyZF/lEyoYAue19r+Guo6I5LVXePuaJr9FRJVrDbCg1mnE X-Received: by 10.98.6.69 with SMTP id 66mr1889213pfg.115.1465339516304; Tue, 07 Jun 2016 15:45:16 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id 4sm37641782pfm.15.2016.06.07.15.45.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Jun 2016 15:45:16 -0700 (PDT) From: Douglas Anderson To: ulf.hansson@linaro.org, kishon@ti.com, Heiko Stuebner , robh+dt@kernel.org Cc: shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Douglas Anderson , pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock Date: Tue, 7 Jun 2016 15:44:41 -0700 Message-Id: <1465339484-969-9-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1465339484-969-1-git-send-email-dianders@chromium.org> References: <1465339484-969-1-git-send-email-dianders@chromium.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As of an earlier change in this series ("Documentation: mmc: sdhci-of-arasan: Add ability to export card clock") the SDHCI driver used on Rockchip SoCs can now expose its clock. Let's now specify that the PHY can use it. Letting the PHY get access to this clock means it can adjust phyctrl_frqsel field appropriately. Although the Rockchip PHY appears slightly different than the reference Arasan one, you can see that the Arasan datasheet [1] had it defined as: Select the frequency range of DLL operation: 3b'000 => 200MHz to 170 MHz 3b'001 => 170MHz to 140 MHz 3b'010 => 140MHz to 110 MHz 3b'011 => 110MHz to 80MHz 3b'100 => 80MHz to 50 MHz 3b'101 => 275Mhz to 250MHz 3b'110 => 250MHz to 225MHz 3b'111 => 225MHz to 200MHz On the Rockchip version of the PHY we have less granularity but the idea is the same. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson --- Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt index 555cb0f40690..fd118b071e5e 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt +++ b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt @@ -7,6 +7,11 @@ Required properties: - reg: PHY register address offset and length in "general register files" +Optional clocks (see ../clock/clock-bindings.txt), specified by name: + - emmcclk: The card clock exported by the SDHCI driver. Although this is + listed as optional (because most boards can get basic functionality + without having access to it), it is strongly suggested. + Example: @@ -20,6 +25,8 @@ grf: syscon@ff770000 { emmcphy: phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; reg = <0xf780 0x20>; + clocks = <&sdhci>; + clock-names = "emmcclk"; #phy-cells = <0>; }; };