From patchwork Mon Jun 20 17:56:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9188453 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9909C601C0 for ; Mon, 20 Jun 2016 18:26:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8C5A82780C for ; Mon, 20 Jun 2016 18:26:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 807F327C14; Mon, 20 Jun 2016 18:26:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 25B8D2780C for ; Mon, 20 Jun 2016 18:26:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755627AbcFTS0q (ORCPT ); Mon, 20 Jun 2016 14:26:46 -0400 Received: from mail-pf0-f171.google.com ([209.85.192.171]:33861 "EHLO mail-pf0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753524AbcFTS0k (ORCPT ); Mon, 20 Jun 2016 14:26:40 -0400 Received: by mail-pf0-f171.google.com with SMTP id h14so41298129pfe.1 for ; Mon, 20 Jun 2016 11:26:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lLIJocY1KZ2robeCeYcgKI3vQOzrfKxkJmorzaolbpY=; b=CS89jYMbJevIGUNjffW0uzZxHn7ojozm8voQrU1NbdHgOYtLGtx5+ZTDFXvNh7qQ7Y wzPeBAqUgEdQ5jit+uL+32busGOoUiOjKbtUVg2kx8561pNk/0+hqt0ec/qv9vjuLZQe /r4vT/1yLYdtnkDS/xtv+SKHvO/z4i4ZIqC0Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lLIJocY1KZ2robeCeYcgKI3vQOzrfKxkJmorzaolbpY=; b=ByA4d8BXAPYqI3d+QK3q3bReJZj/CA39RH2Y7rB+9bwKm3w+Lp09QIBOfXDgOjJ3WX 36LkMzrBfizAyQpMcl3kjOltBpE5N8lw0MMmqo9Q9nehYMyhWwNbbriUomUMe7shST5p UOVn+viNXlq9vO3i+0g64H6It/Q2PabyqV7+1dj8T2isBNiNm8KqBLtTXaZOG6aZZIhZ LRwE7LwpfV9vtVflbwSGV1RCRMBAEa1SOygG7qE6rEaZ+PYFJ2y5hV3+yxHk36wmkU+9 ZyuwZZVKm5L7NZxnu/nSzwPWla3fvPqHGjiipKzI721SCOpeU42tPziNVLKlopBPB3JU x99Q== X-Gm-Message-State: ALyK8tIyMgy+0DyzGGT5iAsRvfMiBbwY6uEo1IHiMbN1lBwuu/DnikVy3R9HCENnCvzjmEAk X-Received: by 10.98.47.129 with SMTP id v123mr22493276pfv.71.1466445635593; Mon, 20 Jun 2016 11:00:35 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id c189sm60250353pfg.19.2016.06.20.11.00.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Jun 2016 11:00:34 -0700 (PDT) From: Douglas Anderson To: ulf.hansson@linaro.org, Heiko Stuebner Cc: kishon@ti.com, robh+dt@kernel.org, shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, groeck@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 03/15] phy: rockchip-emmc: configure default output tap delay Date: Mon, 20 Jun 2016 10:56:42 -0700 Message-Id: <1466445414-11974-4-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1466445414-11974-1-git-send-email-dianders@chromium.org> References: <1466445414-11974-1-git-send-email-dianders@chromium.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Brian Norris The output tap delay controls helps maintain the hold requirements for eMMC. The exact value is dependent on the SoC and other factors, though it isn't really an exact science. But the default of 0 is not very good, as it doesn't give the eMMC much hold time, so let's bump up to 4 (approx 90 degree phase?). If we need to configure this any further (e.g., based on board or speed factors), we may need to consider a device tree representation. Suggested-by: Shawn Lin Signed-off-by: Brian Norris Signed-off-by: Douglas Anderson Acked-by: Kishon Vijay Abraham I Tested-by: Heiko Stuebner --- Changes in v3: - Add Brian's PHY patches into my series Changes in v2: None drivers/phy/phy-rockchip-emmc.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c index f2f75cf69af1..a0b87cc6c818 100644 --- a/drivers/phy/phy-rockchip-emmc.c +++ b/drivers/phy/phy-rockchip-emmc.c @@ -69,6 +69,11 @@ #define PHYCTRL_DR_66OHM 0x2 #define PHYCTRL_DR_100OHM 0x3 #define PHYCTRL_DR_40OHM 0x4 +#define PHYCTRL_OTAPDLYENA 0x1 +#define PHYCTRL_OTAPDLYENA_MASK 0x1 +#define PHYCTRL_OTAPDLYENA_SHIFT 0xb +#define PHYCTRL_OTAPDLYSEL_MASK 0xf +#define PHYCTRL_OTAPDLYSEL_SHIFT 0x7 struct rockchip_emmc_phy { unsigned int reg_offset; @@ -181,6 +186,20 @@ static int rockchip_emmc_phy_power_on(struct phy *phy) PHYCTRL_DR_MASK, PHYCTRL_DR_SHIFT)); + /* Output tap delay: enable */ + regmap_write(rk_phy->reg_base, + rk_phy->reg_offset + GRF_EMMCPHY_CON0, + HIWORD_UPDATE(PHYCTRL_OTAPDLYENA, + PHYCTRL_OTAPDLYENA_MASK, + PHYCTRL_OTAPDLYENA_SHIFT)); + + /* Output tap delay */ + regmap_write(rk_phy->reg_base, + rk_phy->reg_offset + GRF_EMMCPHY_CON0, + HIWORD_UPDATE(4, + PHYCTRL_OTAPDLYSEL_MASK, + PHYCTRL_OTAPDLYSEL_SHIFT)); + /* Power up emmc phy analog blocks */ ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON); if (ret)