From patchwork Mon Jun 20 17:56:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9188431 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D4D8160871 for ; Mon, 20 Jun 2016 18:09:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CAD1D27C39 for ; Mon, 20 Jun 2016 18:09:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BEE1627BFC; Mon, 20 Jun 2016 18:09:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4DA9A27BFC for ; Mon, 20 Jun 2016 18:09:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754588AbcFTSI7 (ORCPT ); Mon, 20 Jun 2016 14:08:59 -0400 Received: from mail-pf0-f181.google.com ([209.85.192.181]:35690 "EHLO mail-pf0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755424AbcFTSIX (ORCPT ); Mon, 20 Jun 2016 14:08:23 -0400 Received: by mail-pf0-f181.google.com with SMTP id c2so56442859pfa.2 for ; Mon, 20 Jun 2016 11:08:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=L5YCNT6XiGvqXROuN10HB2Hoc04hegAmSQEf3szD5bA=; b=TWR+bqPEQE166QGbDFrZM9RJUtFZAh78unDZeKr1mG07TLNSFAACBkY6MjvMw8keQ+ z1VXJ2LJ7YqV9h0w4tNaeKciQ/sR4zw4uae6165+C2hMEUpB+Uv7HnjSheMECNyg+ZY2 FivZfEMJwomrOSTZvTWBZGpATZTBPn4sGyNmk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L5YCNT6XiGvqXROuN10HB2Hoc04hegAmSQEf3szD5bA=; b=hOXeH/P+T9FvLEAUJKboTAYr10ofsg3hWXcJzhArFfB+S9QPYmmt1VpIxm32x7NnkW LhpoMIi/PAhsFY3tpKJ9y5JUl6FsfKf4HO3o9pS76pJasP0nauVrF8okjqEfgAJNlcDY WzsZG5id+SU/RoB0d8S0t2FuEAF1CIP6U30oJz5SdLhIL0aqDsivAeQ4gGx0q7skS2YF xc6la5nBwmhQP5K0Nj8kDlftex3NAbWOwNxPv2qn3uGHWEp8E9YQEL9lhID0MJC5+TX8 KrQxtgZS59I1HMzC6PBK63Wr7pA7UWZJQFKxh37n7qBDXm8lrGE9SUzjJuXT1huLSi1P zZKg== X-Gm-Message-State: ALyK8tJLTQYqKydY62xG+uEYxWkE66Rf8TA+p6xjQ3kqZtpqFaY9e6cQ2tN8peMlR1YYrX5+ X-Received: by 10.98.70.144 with SMTP id o16mr22843889pfi.126.1466445638634; Mon, 20 Jun 2016 11:00:38 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id c189sm60250353pfg.19.2016.06.20.11.00.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Jun 2016 11:00:37 -0700 (PDT) From: Douglas Anderson To: ulf.hansson@linaro.org, Heiko Stuebner Cc: kishon@ti.com, robh+dt@kernel.org, shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, groeck@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 05/15] phy: rockchip-emmc: Increase lock time allowance Date: Mon, 20 Jun 2016 10:56:44 -0700 Message-Id: <1466445414-11974-6-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1466445414-11974-1-git-send-email-dianders@chromium.org> References: <1466445414-11974-1-git-send-email-dianders@chromium.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Previous PHY code waited a fixed amount of time for the DLL to lock at power on time. Unfortunately, the time for the DLL to lock is actually a bit more dynamic and can be longer if the card clock is slower. Instead of waiting a fixed 30 us, let's now dynamically wait until the lock bit gets set. We'll wait up to 10 ms which should be OK even if the card clock is at the super slow 100 kHz. On its own, this change makes the PHY power on code a little more robust. Before this change the PHY was relying on the eMMC code to make sure the PHY was only powered on when the card clock was set to at least 50 MHz before, though this reliance wasn't documented anywhere. This change will be even more useful in future changes where we actually need to be able to wait for a DLL lock at slower clock speeds. Signed-off-by: Douglas Anderson Acked-by: Kishon Vijay Abraham I Reviewed-by: Shawn Lin Tested-by: Heiko Stuebner --- Changes in v3: - Add collected tags Changes in v2: - Indicate that 5.1 ms is calculated (Shawn). drivers/phy/phy-rockchip-emmc.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c index a69f53630e67..2d059c046978 100644 --- a/drivers/phy/phy-rockchip-emmc.c +++ b/drivers/phy/phy-rockchip-emmc.c @@ -85,6 +85,7 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy, { unsigned int caldone; unsigned int dllrdy; + unsigned long timeout; /* * Keep phyctrl_pdb and phyctrl_endll low to allow @@ -137,15 +138,26 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy, PHYCTRL_ENDLL_MASK, PHYCTRL_ENDLL_SHIFT)); /* - * After enable analog DLL circuits, we need an extra 10.2us - * for dll to be ready for work. But according to testing, we - * find some chips need more than 25us. + * After enabling analog DLL circuits docs say that we need 10.2 us if + * our source clock is at 50 MHz and that lock time scales linearly + * with clock speed. If we are powering on the PHY and the card clock + * is super slow (like 100 kHZ) this could take as long as 5.1 ms as + * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms + * Hopefully we won't be running at 100 kHz, but we should still make + * sure we wait long enough. */ - udelay(30); - regmap_read(rk_phy->reg_base, - rk_phy->reg_offset + GRF_EMMCPHY_STATUS, - &dllrdy); - dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; + timeout = jiffies + msecs_to_jiffies(10); + do { + udelay(1); + + regmap_read(rk_phy->reg_base, + rk_phy->reg_offset + GRF_EMMCPHY_STATUS, + &dllrdy); + dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; + if (dllrdy == PHYCTRL_DLLRDY_DONE) + break; + } while (!time_after(jiffies, timeout)); + if (dllrdy != PHYCTRL_DLLRDY_DONE) { pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n"); return -ETIMEDOUT;