From patchwork Mon Jan 2 23:03:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9494289 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B3DC460405 for ; Tue, 3 Jan 2017 00:14:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A77A627CE7 for ; Tue, 3 Jan 2017 00:14:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C18227D13; Tue, 3 Jan 2017 00:14:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 41F7927CE7 for ; Tue, 3 Jan 2017 00:14:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756547AbdABXFk (ORCPT ); Mon, 2 Jan 2017 18:05:40 -0500 Received: from foss.arm.com ([217.140.101.70]:45712 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756162AbdABXEI (ORCPT ); Mon, 2 Jan 2017 18:04:08 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3250E153B; Mon, 2 Jan 2017 15:04:08 -0800 (PST) Received: from slackpad.lan (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AE6113F318; Mon, 2 Jan 2017 15:04:05 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Ulf Hansson Cc: Chen-Yu Tsai , Hans De Goede , Icenowy Zheng , Mark Rutland , Rob Herring , devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] arm64: dts: sun50i: add MMC nodes Date: Mon, 2 Jan 2017 23:03:44 +0000 Message-Id: <1483398226-29321-4-git-send-email-andre.przywara@arm.com> X-Mailer: git-send-email 2.8.2 In-Reply-To: <1483398226-29321-1-git-send-email-andre.przywara@arm.com> References: <1483398226-29321-1-git-send-email-andre.przywara@arm.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 67 +++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index e0dcab8..c680566 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -150,6 +150,32 @@ pins = "PB8", "PB9"; function = "uart0"; }; + + mmc0_pins: mmc0@0 { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + }; + + mmc0_default_cd_pin: mmc0_cd_pin@0 { + pins = "PF6"; + function = "gpio_in"; + bias-pull-up; + }; + + mmc1_pins: mmc1@0 { + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + }; + + mmc2_pins: mmc2@0 { + pins = "PC1", "PC5", "PC6", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", "PC14", + "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + }; }; uart0: serial@1c28000 { @@ -240,6 +266,47 @@ #size-cells = <0>; }; + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu 31>, <&ccu 75>; + clock-names = "ahb", "mmc"; + resets = <&ccu 8>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu 32>, <&ccu 76>; + clock-names = "ahb", "mmc"; + resets = <&ccu 9>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun50i-a64-emmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu 33>, <&ccu 77>; + clock-names = "ahb", "mmc"; + resets = <&ccu 10>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>,