From patchwork Fri Feb 17 02:56:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 9578667 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7A7B4600C5 for ; Fri, 17 Feb 2017 02:59:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6C1D628675 for ; Fri, 17 Feb 2017 02:59:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 60DAB28687; Fri, 17 Feb 2017 02:59:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 578B528675 for ; Fri, 17 Feb 2017 02:59:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754684AbdBQC7r (ORCPT ); Thu, 16 Feb 2017 21:59:47 -0500 Received: from lucky1.263xmail.com ([211.157.147.134]:51663 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754293AbdBQC7r (ORCPT ); Thu, 16 Feb 2017 21:59:47 -0500 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.190]) by lucky1.263xmail.com (Postfix) with ESMTP id 79442B66; Fri, 17 Feb 2017 10:59:43 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id D57283CC; Fri, 17 Feb 2017 10:59:42 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: jh80.chung@samsung.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <66e00c19e46cfea915a9de4131b91083> X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 18502E2TLVF; Fri, 17 Feb 2017 10:59:43 +0800 (CST) From: Shawn Lin To: Jaehoon Chung Cc: Ulf Hansson , linux-mmc@vger.kernel.org, Shawn Lin Subject: [PATCH 2/7] mmc: dw_mmc: move dw_mci_reset forward to avoid declaration Date: Fri, 17 Feb 2017 10:56:40 +0800 Message-Id: <1487300205-202825-3-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1487300205-202825-1-git-send-email-shawn.lin@rock-chips.com> References: <1487300205-202825-1-git-send-email-shawn.lin@rock-chips.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP No functional change intended. Signed-off-by: Shawn Lin --- drivers/mmc/host/dw_mmc.c | 131 +++++++++++++++++++++++----------------------- 1 file changed, 65 insertions(+), 66 deletions(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index a1ddbb8..20fe96c8 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -106,7 +106,6 @@ struct idmac_desc { /* Each descriptor can transfer up to 4KB of data in chained mode */ #define DW_MCI_DESC_DATA_LENGTH 0x1000 -static bool dw_mci_reset(struct dw_mci *host); static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); static int dw_mci_card_busy(struct mmc_host *mmc); static int dw_mci_get_cd(struct mmc_host *mmc); @@ -1674,6 +1673,71 @@ static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, return 0; } +static bool dw_mci_reset(struct dw_mci *host) +{ + u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; + bool ret = false; + + /* + * Resetting generates a block interrupt, hence setting + * the scatter-gather pointer to NULL. + */ + if (host->sg) { + sg_miter_stop(&host->sg_miter); + host->sg = NULL; + } + + if (host->use_dma) + flags |= SDMMC_CTRL_DMA_RESET; + + if (dw_mci_ctrl_reset(host, flags)) { + /* + * In all cases we clear the RAWINTS register to clear any + * interrupts. + */ + mci_writel(host, RINTSTS, 0xFFFFFFFF); + + /* if using dma we wait for dma_req to clear */ + if (host->use_dma) { + u32 status; + + if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, + status, + !(status & SDMMC_STATUS_DMA_REQ), + 1, 500 * USEC_PER_MSEC)) { + dev_err(host->dev, + "%s: Timeout waiting for dma_req to clear during reset\n", + __func__); + goto ciu_out; + } + + /* when using DMA next we reset the fifo again */ + if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) + goto ciu_out; + } + } else { + /* if the controller reset bit did clear, then set clock regs */ + if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { + dev_err(host->dev, + "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", + __func__); + goto ciu_out; + } + } + + if (host->use_dma == TRANS_MODE_IDMAC) + /* It is also recommended that we reset and reprogram idmac */ + dw_mci_idmac_reset(host); + + ret = true; + +ciu_out: + /* After a CTRL reset we need to have CIU set clock registers */ + mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); + + return ret; +} + static const struct mmc_host_ops dw_mci_ops = { .request = dw_mci_request, .pre_req = dw_mci_pre_req, @@ -2837,71 +2901,6 @@ static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) return true; } -static bool dw_mci_reset(struct dw_mci *host) -{ - u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; - bool ret = false; - - /* - * Reseting generates a block interrupt, hence setting - * the scatter-gather pointer to NULL. - */ - if (host->sg) { - sg_miter_stop(&host->sg_miter); - host->sg = NULL; - } - - if (host->use_dma) - flags |= SDMMC_CTRL_DMA_RESET; - - if (dw_mci_ctrl_reset(host, flags)) { - /* - * In all cases we clear the RAWINTS register to clear any - * interrupts. - */ - mci_writel(host, RINTSTS, 0xFFFFFFFF); - - /* if using dma we wait for dma_req to clear */ - if (host->use_dma) { - u32 status; - - if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, - status, - !(status & SDMMC_STATUS_DMA_REQ), - 1, 500 * USEC_PER_MSEC)) { - dev_err(host->dev, - "%s: Timeout waiting for dma_req to clear during reset\n", - __func__); - goto ciu_out; - } - - /* when using DMA next we reset the fifo again */ - if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) - goto ciu_out; - } - } else { - /* if the controller reset bit did clear, then set clock regs */ - if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { - dev_err(host->dev, - "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", - __func__); - goto ciu_out; - } - } - - if (host->use_dma == TRANS_MODE_IDMAC) - /* It is also recommended that we reset and reprogram idmac */ - dw_mci_idmac_reset(host); - - ret = true; - -ciu_out: - /* After a CTRL reset we need to have CIU set clock registers */ - mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); - - return ret; -} - static void dw_mci_cmd11_timer(unsigned long arg) { struct dw_mci *host = (struct dw_mci *)arg;