From patchwork Tue Oct 10 09:30:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chaotian Jing X-Patchwork-Id: 9995491 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DD09060230 for ; Tue, 10 Oct 2017 09:33:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DB171281F9 for ; Tue, 10 Oct 2017 09:33:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CFBA328455; Tue, 10 Oct 2017 09:33:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7FE34281F9 for ; Tue, 10 Oct 2017 09:33:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756176AbdJJJbA (ORCPT ); Tue, 10 Oct 2017 05:31:00 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:33134 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1755746AbdJJJax (ORCPT ); Tue, 10 Oct 2017 05:30:53 -0400 X-UUID: dafcacad30194ee8b7a90783e2b7fea8-20171010 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 972907516; Tue, 10 Oct 2017 17:30:51 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 10 Oct 2017 17:30:49 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 10 Oct 2017 17:30:48 +0800 From: Chaotian Jing To: Ulf Hansson CC: Rob Herring , Mark Rutland , Matthias Brugger , Catalin Marinas , Will Deacon , Chaotian Jing , yong mao , Linus Walleij , Heiner Kallweit , Phong LE , , , , , , Subject: [PATCH v4 04/12] mmc: mediatek: make hs400_tune_response only for mt8173 Date: Tue, 10 Oct 2017 17:30:23 +0800 Message-ID: <1507627831-29323-5-git-send-email-chaotian.jing@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1507627831-29323-1-git-send-email-chaotian.jing@mediatek.com> References: <1507627831-29323-1-git-send-email-chaotian.jing@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP the origin design of hs400_tune_response is for mt8173 because of mt8173 has a special design. for doing that, we add a new member "compatible", by now it's only for mt8173. Signed-off-by: Chaotian Jing --- drivers/mmc/host/mtk-sd.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 643c795..ab2fbbb 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -300,6 +300,7 @@ struct msdc_save_para { struct mtk_mmc_compatible { u8 clk_div_bits; + bool hs400_tune; /* only used for MT8173 */ }; struct msdc_tune_para { @@ -360,18 +361,22 @@ struct msdc_host { static const struct mtk_mmc_compatible mt8135_compat = { .clk_div_bits = 8, + .hs400_tune = false, }; static const struct mtk_mmc_compatible mt8173_compat = { .clk_div_bits = 8, + .hs400_tune = true, }; static const struct mtk_mmc_compatible mt2701_compat = { .clk_div_bits = 12, + .hs400_tune = false, }; static const struct mtk_mmc_compatible mt2712_compat = { .clk_div_bits = 12, + .hs400_tune = false, }; static const struct of_device_id msdc_of_ids[] = { @@ -666,7 +671,8 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) host->base + PAD_CMD_TUNE); } - if (timing == MMC_TIMING_MMC_HS400) + if (timing == MMC_TIMING_MMC_HS400 && + host->dev_comp->hs400_tune) sdr_set_field(host->base + PAD_CMD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, host->hs400_cmd_int_delay); @@ -1594,7 +1600,8 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) struct msdc_host *host = mmc_priv(mmc); int ret; - if (host->hs400_mode) + if (host->hs400_mode && + host->dev_comp->hs400_tune) ret = hs400_tune_response(mmc, opcode); else ret = msdc_tune_response(mmc, opcode);