From patchwork Tue Oct 10 09:30:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chaotian Jing X-Patchwork-Id: 9995495 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9DA5E60230 for ; Tue, 10 Oct 2017 09:35:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9827F28448 for ; Tue, 10 Oct 2017 09:35:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8D0EC28455; Tue, 10 Oct 2017 09:35:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F31DC28449 for ; Tue, 10 Oct 2017 09:35:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756001AbdJJJdt (ORCPT ); Tue, 10 Oct 2017 05:33:49 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:46875 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1755349AbdJJJbA (ORCPT ); Tue, 10 Oct 2017 05:31:00 -0400 X-UUID: 22d6964b8182456fbedd35854c474144-20171010 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1647885227; Tue, 10 Oct 2017 17:30:57 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 10 Oct 2017 17:30:56 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 10 Oct 2017 17:30:55 +0800 From: Chaotian Jing To: Ulf Hansson CC: Rob Herring , Mark Rutland , Matthias Brugger , Catalin Marinas , Will Deacon , Chaotian Jing , yong mao , Linus Walleij , Heiner Kallweit , Phong LE , , , , , , Subject: [PATCH v4 07/12] mmc: mediatek: add busy_check support Date: Tue, 10 Oct 2017 17:30:26 +0800 Message-ID: <1507627831-29323-8-git-send-email-chaotian.jing@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1507627831-29323-1-git-send-email-chaotian.jing@mediatek.com> References: <1507627831-29323-1-git-send-email-chaotian.jing@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP bit7 of PATCH_BIT1 has different meaning in new design, to compatible with previous platform, clear this bit in new platform. Signed-off-by: Chaotian Jing --- drivers/mmc/host/mtk-sd.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index ebec2b4..187fe8a 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -316,6 +316,7 @@ struct mtk_mmc_compatible { bool pad_tune0; bool async_fifo; bool data_tune; + bool busy_check; }; struct msdc_tune_para { @@ -380,6 +381,7 @@ struct msdc_host { .pad_tune0 = false, .async_fifo = false, .data_tune = false, + .busy_check = false, }; static const struct mtk_mmc_compatible mt8173_compat = { @@ -388,6 +390,7 @@ struct msdc_host { .pad_tune0 = false, .async_fifo = false, .data_tune = false, + .busy_check = false, }; static const struct mtk_mmc_compatible mt2701_compat = { @@ -396,6 +399,7 @@ struct msdc_host { .pad_tune0 = true, .async_fifo = true, .data_tune = true, + .busy_check = false, }; static const struct mtk_mmc_compatible mt2712_compat = { @@ -404,6 +408,7 @@ struct msdc_host { .pad_tune0 = true, .async_fifo = true, .data_tune = true, + .busy_check = true, }; static const struct of_device_id msdc_of_ids[] = { @@ -1280,6 +1285,8 @@ static void msdc_init_hw(struct msdc_host *host) sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); writel(0xffff4089, host->base + MSDC_PATCH_BIT1); sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); + if (host->dev_comp->busy_check) + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); if (host->dev_comp->async_fifo) { sdr_set_field(host->base + MSDC_PATCH_BIT2, MSDC_PB2_RESPWAIT, 3);