From patchwork Wed Dec 19 23:42:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10738301 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DB480924 for ; Wed, 19 Dec 2018 23:42:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA5EE2886B for ; Wed, 19 Dec 2018 23:42:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BBA4C28882; Wed, 19 Dec 2018 23:42:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5643E2886B for ; Wed, 19 Dec 2018 23:42:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728479AbeLSXmZ (ORCPT ); Wed, 19 Dec 2018 18:42:25 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19000 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729876AbeLSXmY (ORCPT ); Wed, 19 Dec 2018 18:42:24 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 19 Dec 2018 15:42:13 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 19 Dec 2018 15:42:23 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 19 Dec 2018 15:42:23 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 19 Dec 2018 23:42:23 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 19 Dec 2018 23:42:22 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.103.52]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 19 Dec 2018 15:42:22 -0800 From: Sowjanya Komatineni To: , , , , , , CC: , , , , Sowjanya Komatineni Subject: [PATCH V4 3/4] arm64: dtsi: Fix SDMMC address range Date: Wed, 19 Dec 2018 15:42:17 -0800 Message-ID: <1545262938-20636-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545262938-20636-1-git-send-email-skomatineni@nvidia.com> References: <1545262938-20636-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1545262934; bh=CFBtF6ZaKNyqKgjWa+hPoclDVuRehYmyqcZmFtTTkGs=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Ixy2UxbNdZXRhr1k0H9dvUimx8QjMfNRkERGA9c56fK7bP1rKzb0KVhlUCHv2eZs4 1nSzMcldLKVqxIloyuGVLRlB0vA3oULObicrVmYVmDKfxDoZ8P8KxIXprxLgOeJri1 jGTb1xCefnyYY3kilF6qOzJdwlSqXZOTr+sG0pFIM0pMi4dwx/YkXSN+AAyx0J9goI 576TsH/s94gp+yQt9yWJSGDbyxM9yQSFT+uWNuQ5AjwojjTRXcIeWjX5FVCOiLcwDu F9Nw7FJjSJWv3AfLLDcU6034cucUEQCwVmX3h9yWhrX13dBANSKZk3YmYK38Jf8he4 3VFtJgiqjRhkA== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch fixes the SDMMC Controllers address space to be exact defined register address range as per the design. SDMMC Controller supporting Command Queue has CQHCI registers at offset 0xF000. This fix helps to identify the Tegra SDMMC Controllers supporting Command Queue based on the size of address space. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 6 +++--- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 2f3c8e29520d..6fda3d6a7f3d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -231,7 +231,7 @@ sdmmc1: sdhci@3400000 { compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03400000 0x0 0x10000>; + reg = <0x0 0x03400000 0x0 0x220>; interrupts = ; clocks = <&bpmp TEGRA186_CLK_SDMMC1>; clock-names = "sdhci"; @@ -256,7 +256,7 @@ sdmmc2: sdhci@3420000 { compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03420000 0x0 0x10000>; + reg = <0x0 0x03420000 0x0 0x220>; interrupts = ; clocks = <&bpmp TEGRA186_CLK_SDMMC2>; clock-names = "sdhci"; @@ -276,7 +276,7 @@ sdmmc3: sdhci@3440000 { compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03440000 0x0 0x10000>; + reg = <0x0 0x03440000 0x0 0x220>; interrupts = ; clocks = <&bpmp TEGRA186_CLK_SDMMC3>; clock-names = "sdhci"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c2091bb16546..6510ef6492b1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -295,7 +295,7 @@ sdmmc1: sdhci@3400000 { compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; - reg = <0x03400000 0x10000>; + reg = <0x03400000 0x220>; interrupts = ; clocks = <&bpmp TEGRA194_CLK_SDMMC1>; clock-names = "sdhci"; @@ -306,7 +306,7 @@ sdmmc3: sdhci@3440000 { compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; - reg = <0x03440000 0x10000>; + reg = <0x03440000 0x220>; interrupts = ; clocks = <&bpmp TEGRA194_CLK_SDMMC3>; clock-names = "sdhci";