| Message ID | 1546457808-18270-2-git-send-email-skomatineni@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | HW Command Queue support for Tegra SDMMC | expand |
On Wed, Jan 02, 2019 at 11:36:47AM -0800, Sowjanya Komatineni wrote: > This patch fixes the SDMMC Controllers address space to be exact > defined register address range as per the design. > > SDMMC Controller supporting Command Queue has CQHCI registers at > offset 0xF000. > > This fix helps to identify the Tegra SDMMC Controllers supporting > Command Queue based on the size of address space. > > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra186.dtsi | 6 +++--- > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++-- > 2 files changed, 5 insertions(+), 5 deletions(-) After applying these patches I'm having second thoughts about the DT aspect of this. I know you and Timo had originally argued to advertise the capability via an extra property in DT instead of updating the reg property. In retrospect, I think that's the right thing to do, after all. The problem I'm running into is that if I apply patch 2/2 without the first patch, then both Jetson TX2 and Jetson AGX Xavier crash on boot because they try to access these registers (the I/O memory size is 0x10000 for all controllers). So we're effectively breaking ABI with existing device trees. I don't know of a way to work around that other than the separate property. Would you mind changing the series to contain: 1) a patch updating the device tree bindings with the new optional property that would mark SDMMC4 as CQE capable (make sure to Cc devicetree@vger.kernel.org on that patch) 2) replace this patch by one which only adds the new "supports-cqe" property 3) update the second patch to make the decision based on the flag rather than the I/O memory size Sorry for the back and forth on this. I evidently hadn't thought this through. Thierry
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 2f3c8e29520d..6fda3d6a7f3d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -231,7 +231,7 @@ sdmmc1: sdhci@3400000 { compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03400000 0x0 0x10000>; + reg = <0x0 0x03400000 0x0 0x220>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA186_CLK_SDMMC1>; clock-names = "sdhci"; @@ -256,7 +256,7 @@ sdmmc2: sdhci@3420000 { compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03420000 0x0 0x10000>; + reg = <0x0 0x03420000 0x0 0x220>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA186_CLK_SDMMC2>; clock-names = "sdhci"; @@ -276,7 +276,7 @@ sdmmc3: sdhci@3440000 { compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03440000 0x0 0x10000>; + reg = <0x0 0x03440000 0x0 0x220>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA186_CLK_SDMMC3>; clock-names = "sdhci"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c2091bb16546..6510ef6492b1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -295,7 +295,7 @@ sdmmc1: sdhci@3400000 { compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; - reg = <0x03400000 0x10000>; + reg = <0x03400000 0x220>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SDMMC1>; clock-names = "sdhci"; @@ -306,7 +306,7 @@ sdmmc3: sdhci@3440000 { compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; - reg = <0x03440000 0x10000>; + reg = <0x03440000 0x220>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SDMMC3>; clock-names = "sdhci";
This patch fixes the SDMMC Controllers address space to be exact defined register address range as per the design. SDMMC Controller supporting Command Queue has CQHCI registers at offset 0xF000. This fix helps to identify the Tegra SDMMC Controllers supporting Command Queue based on the size of address space. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 6 +++--- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-)